公开(公告)号：US20140113410A1

公开(公告)日：2014-04-24

申请号：US13655036

申请日：2012-10-18

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： How Yuan Hwang ,  Jay Maghirang ,  Yaohuang Huang ,  Kim-Yong Goh ,  Phone Maw Hla ,  Edmond Soon

IPC: H01L21/60

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer.

Abstract translation: 本公开的实施例涉及在晶片级制造系统级封装。 具体地，各种实施例涉及将第一晶片粘附到第二晶片并将焊球粘附到第一晶片的接触焊盘。 在一个实施例中，提供具有第一和第二表面的第一晶片。 第一晶片包括位于第一表面上的接合焊盘，其耦合到位于第一晶片中的相应半导体器件。 提供了具有位于其中的电气部件的第二晶片。 在第一晶片和第二晶片中的至少一个上提供导电粘合剂。 导电球设置在第一晶片的第一表面上的接合焊盘上。 导电球和导电粘合剂被加热以使导电球粘附到接合焊盘和导电粘合剂以将第一晶片粘附到第二晶片。

公开(公告)号：US20140103521A1

公开(公告)日：2014-04-17

申请号：US13652937

申请日：2012-10-16

Applicant: STMICROELECTRONICS PTE. LTD

Inventor： Yonggang Jin ,  How Yuan HWANG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.

Abstract translation: 电子设备可以包括底部互连层和由底部互连层承载的集成电路（IC）。 电子设备还可以包括底部互连层上的封装材料并横向包围IC。 电子器件还可以包括穿过封装材料的底部互连层上的导电柱。 至少一个导电柱和封装材料的相邻部分可以相对于IC和封装材料的相邻部分具有减小的高度，并且可以限定至少一个接触凹部。 所述至少一个接触凹部可以与所述封装材料的周边向内间隔开。

公开(公告)号：US20140091443A1

公开(公告)日：2014-04-03

申请号：US14032075

申请日：2013-09-19

Applicant: STMicroelectronics Pte Ltd ,  STMicroelectronics (Malta) Ltd

Inventor： Roseanne Duca ,  Kim-Yong Goh ,  Xueren Zhang ,  Kevin Formosa

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49541 ,  G01P1/023 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/1815 ,  H05K3/303 ,  H05K3/3421 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/45099

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract translation: 半导体器件的表面贴装封装具有：封装，容纳至少一个包含半导体材料的管芯; 以及电接触引线，从封装凸出以电耦合到电路板的接触焊盘; 封装具有设计成面向电路板的顶表面的主面，该主面具有设计成用于机械耦合到电路板的耦合特征，以增加安装封装的谐振频率。 耦合特征设想至少一个第一耦合凹槽，其限定在从主面开始的封装内，被设计成由固定到电路板的对应耦合元件接合，从而限制安装的封装的移动。

公开(公告)号：US08644053B2

公开(公告)日：2014-02-04

申请号：US13953626

申请日：2013-07-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Olivier Le Neel

IPC: G11C11/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。

公开(公告)号：US20130314972A1

公开(公告)日：2013-11-28

申请号：US13953626

申请日：2013-07-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Olivier Le Neel

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。

公开(公告)号：EP4227992A3

公开(公告)日：2023-12-06

申请号：EP23151738.4

申请日：2023-01-16

Applicant: STMicroelectronics Pte Ltd.

Inventor： CHEN, Yong ,  GANI, David

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package includes a die and a first lamination layer on the die with openings through the first lamination layer. A redistribution layer is on the first lamination layer and extends through the openings to the die. A plurality of conductive extensions are on the redistribution layer with each stud including a first surface on the redistribution layer, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface. A second lamination layer is on the redistribution layer and the first lamination layer with the die encapsulated in molding compound. The second lamination layer is removed around the conductive extensions to expose the second surface and at least a portion of the sidewall of each stud to improve solder bond strength when mounting the package to a circuit board.

公开(公告)号：EP4216264A1

公开(公告)日：2023-07-26

申请号：EP23151728.5

申请日：2023-01-16

Applicant: STMicroelectronics Pte Ltd.

Inventor： YIM, Churn Weng ,  CASTORINA, Maurizio Gabriele ,  NGWAN, Voon Cheng ,  YONG, Yean Ching ,  ADNAN, Ditto ,  TAHIR, Fadhillawati

IPC: H01L23/00

Abstract: A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.

公开(公告)号：EP3955311A1

公开(公告)日：2022-02-16

申请号：EP21189249.2

申请日：2021-08-03

Applicant: STMicroelectronics Pte Ltd.

Inventor： ADNAN, Ditto ,  CASTORINA, Maurizio Gabriele ,  NGWAN, Voon Cheng ,  TAHIR, Fadhillawati

IPC: H01L29/40 ,  H01L21/336 ,  H01L29/78

Abstract: A semiconductor substrate (12) has a trench (18) extending from a front surface (14) and including a lower part and an upper part. A first insulation layer (20) lines the lower part of the trench, and a first conductive material (22) in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer (130) lines sidewalls of the upper part of said trench. A third insulating layer (132) lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material (32) fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor (100) that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.

公开(公告)号：EP3852139A3

公开(公告)日：2021-09-08

申请号：EP20215558.6

申请日：2020-12-18

Applicant: STMicroelectronics Pte Ltd.

Inventor： GANI, David

IPC: H01L23/485 ,  H01L21/60

Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) (100, 200, 300) with bumps with various combinations of conductive structures such as solder (118, 120, 214, 216, 314, 316) and under bump metallizations (UBMs) (112, 117, 311, 312) having different structures and different amounts of solder (118, 120, 214, 216, 314, 316) coupled to the UBMs (112, 117, 311, 312). Although the bumps have different structures and the volume (height) of solder (118, 120, 214, 216, 314, 316) differs, the total standoff height along the WLCSP (100, 200, 300) remains substantially the same. Each portion of solder (118, 120, 214, 216, 314, 316) includes a point furthest away from an active surface (103, 203, 303) of a die (102, 202, 302) of the WLCSP (100, 200, 300). Each point of each respective portion of solder (118, 120, 214, 216, 314, 316) is co-planar with each other respective point of the other respective portions of solder (118, 120, 214, 216, 314, 316). Additionally, the bumps with different structures are positioned accordingly on the active surface of the die (102, 202, 302) of the WLCSP (100, 200, 300) to reduce failures that may result from the WLCSP (100, 200, 300) being exposed to thermal cycling or the WLCSP (100, 200, 300) being dropped, or because of electromigration, in that less solder (118, 120, 214, 216, 314, 316) is used for bumps at corners of the WLCSP (100, 200, 300). The bumps with less solder comprise an additional contact structure (116, 212, 310) on which the solder (120, 214, 314) is formed. The bumps may be placed on a conductive redistribution layer (108, 208) or on contact pads (304) on the active surface (303) of the die (302) without a redistribution layer. During the manufacturing process, the conductive material (428) of the conductive structures (the solder) is filled in openings (424, 426) of a stencil (422), followed by removing excess portions of the conductive material (428) on the stencil (422) by a squeegee (430).

公开(公告)号：EP2423949A2

公开(公告)日：2012-02-29

申请号：EP11178593.7

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd.

Inventor： Le Neel, Olivier ,  Leng, Calvin

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L28/24 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a thin film resistor (102) having a first resistor layer (103a) having a first temperature coefficient of resistance and a second resistor layer (103b) on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 5-15 nm and the second resistor layer may have a thickness in the range of 2-5 nm.

Abstract translation: 本公开涉及一种薄膜电阻器（102），其具有第一电阻层（103a）和第二电阻层（103b），第一电阻层（103a）具有第一温度系数电阻，第二电阻层具有第二温度 电阻系数与第一温度系数电阻不同。 电阻的第一温度系数可以为正，而第二温度系数为负。 第一电阻层的厚度可以在5-15nm的范围内，第二电阻层的厚度可以在2-5nm的范围内。