公开(公告)号：EP2423949A2

公开(公告)日：2012-02-29

申请号：EP11178593.7

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd.

Inventor： Le Neel, Olivier ,  Leng, Calvin

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L28/24 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a thin film resistor (102) having a first resistor layer (103a) having a first temperature coefficient of resistance and a second resistor layer (103b) on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 5-15 nm and the second resistor layer may have a thickness in the range of 2-5 nm.

Abstract translation: 本公开涉及一种薄膜电阻器（102），其具有第一电阻层（103a）和第二电阻层（103b），第一电阻层（103a）具有第一温度系数电阻，第二电阻层具有第二温度 电阻系数与第一温度系数电阻不同。 电阻的第一温度系数可以为正，而第二温度系数为负。 第一电阻层的厚度可以在5-15nm的范围内，第二电阻层的厚度可以在2-5nm的范围内。

公开(公告)号：EP2474980B1

公开(公告)日：2019-05-22

申请号：EP11195540.7

申请日：2011-12-23

Applicant: STMicroelectronics Pte Ltd.

Inventor： Le Neel, Olivier ,  Jimenez, Jean

IPC: G11C13/00 ,  G11C11/56 ,  G11C17/18 ,  H01L27/24 ,  H01L45/00 ,  H01L27/10 ,  H01L27/105 ,  H01L49/02

公开(公告)号：EP2474980A2

公开(公告)日：2012-07-11

申请号：EP11195540.7

申请日：2011-12-23

Applicant: STMicroelectronics Pte Ltd.

Inventor： Le Neel, Olivier ,  Jimenez, Jean

IPC: G11C13/00 ,  G11C11/56 ,  G11C17/18

CPC classification number: G11C13/0069 ,  G11C11/5692 ,  G11C17/18 ,  G11C2013/008 ,  G11C2213/33 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/14 ,  H01L45/148

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有可调电阻器和加热元件。 电介质材料将加热元件与可调电阻器分开。 加热元件通过向其施加热量来改变电阻器的电阻。 可调电阻器的电阻的大小表示存储在存储单元中的数据的值。

公开(公告)号：EP2423948A3

公开(公告)日：2012-08-29

申请号：EP11178590.3

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd.

Inventor： Ng, Hui Chong Vince ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit (100) having a substrate (108) and a first and a second interconnect structure (104a,b) over the substrate. Each interconnect structure has a first conductive layer (106) over the substrate and a second conductive layer (124) over the first conductive layer. The integrated circuit also includes a thin film resistor (102) over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.

公开(公告)号：EP2423948A2

公开(公告)日：2012-02-29

申请号：EP11178590.3

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd.

Inventor： Ng, Hui Chong Vince ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit (100) having a substrate (108) and a first and a second interconnect structure (104a,b) over the substrate. Each interconnect structure has a first conductive layer (106) over the substrate and a second conductive layer (124) over the first conductive layer. The integrated circuit also includes a thin film resistor (102) over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.

Abstract translation: 本发明涉及在具有基板（108）和第一和第二互连结构（104A，b）在基板的集成电路（100）。 每一个互连结构具有超过基板和在所述第一导电层的第二导电层（124）的第一导电层（106）。 因此，该集成电路包括一个薄膜电阻器（102）在第一和没有导电连接第一和第二互连结构的第一层的第二互连结构之间的衬底的一部分。

公开(公告)号：EP2423950B1

公开(公告)日：2020-04-15

申请号：EP11178597.8

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics, Inc.

Inventor： Lim, Ting Fang ,  Niu, Chengyu ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01C1/148 ,  H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L21/768 ,  H01C7/00

公开(公告)号：EP2474980A3

公开(公告)日：2014-04-09

申请号：EP11195540.7

申请日：2011-12-23

Applicant: STMicroelectronics Pte Ltd.

Inventor： Le Neel, Olivier ,  Jimenez, Jean

IPC: G11C13/00 ,  G11C11/56 ,  G11C17/18

CPC classification number: G11C13/0069 ,  G11C11/5692 ,  G11C17/18 ,  G11C2013/008 ,  G11C2213/33 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/14 ,  H01L45/148

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell.

公开(公告)号：EP2423950A3

公开(公告)日：2013-05-01

申请号：EP11178597.8

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics, Inc.

Inventor： Lim, Ting Fang ,  Niu, Chengyu ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L21/768 ,  H01C7/00

Abstract: The present disclosure is directed to a thin film resistor structure (100) that includes a resistive element (102) electrically connecting first conductor layers (106a,b) of adjacent interconnect structures (104a,b). The resistive element is covered by a dielectric cap layer (105) that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer (124) over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.

公开(公告)号：EP2423949A3

公开(公告)日：2013-05-01

申请号：EP11178593.7

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd.

Inventor： Le Neel, Olivier ,  Leng, Calvin

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L28/24 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a thin film resistor (102) having a first resistor layer (103a) having a first temperature coefficient of resistance and a second resistor layer (103b) on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 5-15 nm and the second resistor layer may have a thickness in the range of 2-5 nm.

公开(公告)号：EP2423950A2

公开(公告)日：2012-02-29

申请号：EP11178597.8

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics Inc

Inventor： Lim, Ting Fang ,  Niu, Chengyu ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/64

Abstract: The present disclosure is directed to a thin film resistor structure (100) that includes a resistive element (102) electrically connecting first conductor layers (106a,b) of adjacent interconnect structures (104a,b). The resistive element is covered by a dielectric cap layer (105) that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer (124) over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.

Abstract translation: 本发明涉及的薄膜电阻器结构（100）包括一电阻性元件那样（102），其电连接第一导体层（106A，B）相邻的互连结构（104A，B）。 所述电阻元件由介电覆盖层覆盖（105）确实用作稳定剂和散热器为电阻元件。 每个互连件包括在所述第一导电层的第二导体层（124）。 薄膜电阻器包括由硅氮化物帽层覆盖的硅铬电阻元件。