公开(公告)号：WO1996008871A1

公开(公告)日：1996-03-21

申请号：PCT/US1995011718

申请日：1995-09-14

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CAMPBELL, John, G. ,  WONG, Ban, Pak

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03K19/0175

CPC classification number: H03K19/0136 ,  H03K19/00353 ,  H03K19/017581

Abstract: An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor (Q1, Q2) coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices (N5-N8) coupled between the common output node and the base of the pull-down bipolar transistor (Q2). A second set of parallel MOS devices (P1-P4) are coupled between the base of the pull-up output stage bipolar transistor (Q1) and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Abstract translation: 公开了一种控制其输出信号的转换速率的输出缓冲器。 该缓冲器包括一个上拉电阻和一个下拉双极晶体管（Q1，Q2），耦合在VDD和VSS之间串联的公共输出节点。 缓冲器还包括耦合在公共输出节点和下拉双极晶体管（Q2）的基极之间的第一组并联MOS器件（N5-N8）。 第二组并联MOS器件（P1-P4）耦合在上拉输出级双极晶体管（Q1）的基极和VDD之间。 每组MOS器件的栅极耦合到数字选择信号。 每个上拉和下拉晶体管（当它们被使能时）驱动基极的电流量由数字选择信号使能的MOS器件的数量决定。 因此，本发明的缓冲器能够调节其输出信号的转换速率以适应耦合到公共输出节点的不同负载。

公开(公告)号：WO1995020223A1

公开(公告)日：1995-07-27

申请号：PCT/US1995000816

申请日：1995-01-20

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak ,  CAMPBELL, John, G.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G11C11/41

CPC classification number: G11C11/41

Abstract: A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell comprises two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal. A differential current signal representing the data stored in the memory cell is established in the complementary bit lines when the current source is selected and current is allowed to flow through one of the bipolar signal converters. The third and fourth ECL voltage potentials are chosen such that they ensure that the bipolar signal converters are not driven into saturation. In this way, read times are optimized. In addition, read times are reduced since peak-to-peak voltages of the current mode differential signal established across the complementary bit lines are reduced.

Abstract translation: 公开了一种电流模式存取BiCMOS存储单元。 存储单元包括用于存储对应于第一和第二逻辑电平的第一和第二CMOS电压电位VDD和VSS的CMOS存储单元。 存储单元包括耦合在VDD和VSS之间的两个CMOS反相器。 存储单元耦合到转换电路。 转换电路耦合在第三和第四ECL工作电位之间。 它用于将第一和第二CMOS电压电位转换为第三和第四工作电位。 第三和第四电压电位耦合到两个双极性信号转换器的基极。 双极性信号转换器的发射极耦合到可选择的电流源，并且双极性信号转换器的集电极耦合到互补位线。 可选择的电流源响应于读取字信号。 当选择电流源并且允许电流流过双极型信号转换器之一时，表示存储在存储单元中的数据的差分电流信号被建立在互补位线中。 选择第三和第四ECL电压电位，使得它们确保双极性信号转换器不被驱动到饱和。 以这种方式，优化了阅读时间。 此外，由于在互补位线上建立的电流模式差分信号的峰 - 峰电压减小，所以读取时间减少。

公开(公告)号：WO1994029870A1

公开(公告)日：1994-12-22

申请号：PCT/US1994004615

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  ROBINSON, Timothy, B. ,  CAMPBELL, John, G. ,  HANSEN, Craig, C.

IPC: G11C07/00

CPC classification number: G11C7/1039 ,  G11C5/025

Abstract: A large burst mode memory (10) accessing system (15) includes N discrete sub-memories (11, 12) and three main I/O ports (17, 18, 19). Data is stored in the sub-memories so that the sub-memories (11, 12) are accessed depending on their proximity to the main I/O ports (17, 18, 19). Three parallel pipelines (1, 2, 3) provide a data path to/from the main I/O ports (17, 18, 19) and the sub-memories (11, 12). The first pipeline (1) functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline (2) functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline (3) propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

Abstract translation: 大型突发模式存储器（10）访问系统（15）包括N个离散子存储器（11,12）和三个主要I / O端口（17,18,19）。 数据被存储在子存储器中，使得子存储器（11,12）根据其与主I / O端口（17,18,19）的接近度被访问。 三条并行的管道（1,2,3）为主I / O端口（17,18,19）和子存储器（11,12）提供数据路径。 第一管线（1）用于将地址/控制信号耦合到存储器，使得相邻子存储器以半周期间隔被访问。 第二管线（2）用于将访问数据从子存储器传播到主I / O端口，使得每个连续时钟周期从主输出端口输出数据。 第三流水线（3）将写数据传播到存储器，使得在连续时钟周期的第三流水线的输入处呈现的数据被写入连续的子存储器。 冗余电路保留数据完整性，无需存储器访问中断。

公开(公告)号：WO1993017461A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001203

申请日：1993-02-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L29/72

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0826 ,  Y10S257/927

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region (11) formed above a more heavily-doped n+ layer (12). Directly above the collector is a p-type base which has an extrinsic region (17) disposed laterally about an intrinsic region (18). An n+ emitter (20) is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region (15) disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract translation: 显示抑制Kirk效应的双极结型晶体管（BJT）包括形成在更重掺杂的n +层（12）上方的轻掺杂的n型集电极区域（11）。 集电极的正上方是p型基体，其具有围绕本征区域横向设置的非本征区域（17）。 n +发射极（20）位于本征基极区的正上方。 BJT还包括直接位于本征基极区下方的局部n +区（15），这显着增加了晶体管的电流处理能力。

公开(公告)号：WO1992020160A1

公开(公告)日：1992-11-12

申请号：PCT/US1992003512

申请日：1992-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A. ,  ROSSEEL, Geert

IPC: H03K17/16

CPC classification number: H03K19/09448

Abstract: A BiCMOS logic circuit (20) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (VIN) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a p-channel metal-oxide-semiconductor (PMOS) transistor (26, 27). An emitter follower (33 or 34), having its base coupled to the collector of one of the bipolar transistors and its collector connected to the first power supply potential (GND), provides the output signal. NMOS transistors (24, 36, 37) are used as current sources for biasing the emitter-coupled pair and the emitter follower. A circuit means provides a feedback signal coupled to the gates of the PMOS transistors for dynamically controlling the load resistance presented to said emitter coupled pair.

公开(公告)号：WO1991020084A1

公开(公告)日：1991-12-26

申请号：PCT/US1991004085

申请日：1991-06-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: G11C13/06

CPC classification number: G11C11/18 ,  G02F1/09 ,  G02F1/19 ,  G11C7/005 ,  G11C13/04

Abstract: An optical modulator utilizing a magnetic semiconductor device, whose operation is based on the Hall effect, includes a magnetic material (33) formed on a semiconductor substrate (27). When an incoming beam of light (105) having a dominant polarization direction is directed onto the magnetic material (33) it becomes modulated. The result is an outgoing beam of light (106) which has a rotated plane of polarization when compared to the dominant polarization direction. The direction of the rotated plane of polarization is indicative of the information stored in the magnetic material (33). The modulator of the present invention further includes a means for writing the information to the magnetic material and a semiconductor sensor means (35) for electrically verifying the contents of the magnetic material (33).

公开(公告)号：WO1991011006A1

公开(公告)日：1991-07-25

申请号：PCT/US1991000331

申请日：1991-01-16

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: G11C11/18

CPC classification number: G11C11/18

Abstract: A non-volatile, static magnetic memory device (10), whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch (33) which stores data in the form of a magnetic field, a semiconductor Hall bar (14, 15, and 17) and a pair of integrally-formed bipolar transistors (28 and 29) used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases (18 and 19) of the bipolar transistors (28 and 29) are ohmically coupled to the Hall bar to sense the Hall voltage, the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.

公开(公告)号：AU7595596A

公开(公告)日：1997-04-30

申请号：AU7595596

申请日：1996-10-10

Applicant: MICROUNITY SYSTEMS ENGINEERING INC

Inventor： HANSEN CRAIG C

IPC: G06F12/02 ,  G06F12/10 ,  G06F12/14 ,  G06F19/00

Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache bit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

公开(公告)号：AU1756692A

公开(公告)日：1992-11-02

申请号：AU1756692

申请日：1992-03-31

Applicant: MICROUNITY SYSTEMS ENGINEERING INC

Inventor： JAMES A MATTHEWS

IPC: F28F3/04 ,  F28F3/12 ,  H01L23/473

公开(公告)号：AU3786193A

公开(公告)日：1993-09-13

申请号：AU3786193

申请日：1993-02-23

Applicant: MICROUNITY SYSTEMS ENGINEERING INC

Inventor： ROSSEEL GEERT ,  HERNDON WILLIAM H ,  MATTHEWS JAMES A

IPC: H03K19/003 ,  H03K17/14 ,  H03K17/567 ,  H03K17/60 ,  H03K19/08 ,  H03K19/086 ,  H03K19/0944 ,  H03K17/16

Abstract: An improved BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal providing a variable load resistance. The control signal is preferably provided by a feedback network which maintains a constant voltage swing across the network over temperature.