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    31.
    发明专利
    Filter 审中-公开
    过滤

    公开(公告)号：JP2005286778A

    公开(公告)日：2005-10-13

    申请号：JP2004099251

    申请日：2004-03-30

    Applicant: Niigata Seimitsu Kk ,  Toyota Industries Corp ,  新潟精密株式会社 ,  株式会社豊田自動織機

    Inventor： AOYAMA TAKASHI ,  MIYAGI HIROSHI

    IPC: H03H11/04

    Abstract: PROBLEM TO BE SOLVED: To form a filter with large attenuation using a gmC filter on a MOS integrated circuit substrate.
    SOLUTION: The filter 11 comprises the gmC filter 13 which comprises a plurality of mutual conductance amplifiers gm1, gm2, ..., and capacitors C1, C2, ..., and has a characteristic to pass a signal of a special bandwidth; a LPF 12 which has a characteristic to attenuate a signal of high side of a stop bandwidth, and a HPF 14 which has a characteristic to attenuate a signal of low band side of a stop bandwidth. Since the filter 11 is composed as stated above, it is possible to form a band pass filter in which attenuation in the stop bandwidth is large, on the MOS integrated circuit substrate.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：使用MOS集成电路基板上的gmC滤波器形成具有大衰减的滤波器。 解决方案：滤波器11包括gmC滤波器13，其包括多个互导放大器gm1，gm2，...和电容器C1，C2，...，并具有通过特殊信号的特性 带宽; 具有衰减停止带宽的高侧的信号的特性的LPF12以及具有衰减停止带宽的低频带侧的信号的特性的HPF14。 由于滤波器11如上所述构成，所以可以在MOS集成电路基板上形成阻带宽度的衰减大的带通滤波器。 版权所有（C）2006，JPO＆NCIPI

    Semiconductor integrated circuit
    32.
    发明专利
    Semiconductor integrated circuit 审中-公开
    半导体集成电路

    公开(公告)号：JP2005269139A

    公开(公告)日：2005-09-29

    申请号：JP2004077560

    申请日：2004-03-18

    Applicant: Niigata Seimitsu Kk ,  Toyota Industries Corp ,  新潟精密株式会社 ,  株式会社豊田自動織機

    Inventor： AOYAMA TAKASHI ,  MIYAGI HIROSHI

    IPC: H03D1/18 ,  H03F3/347 ,  H04B1/16

    Abstract: PROBLEM TO BE SOLVED: To reduce the unevenness of the gain of a detection circuit formed on a MOS integrated circuit.
    SOLUTION: N-channel MOS transistors Q1, Q2 are connected at sources to resistors R1, R2. R1=R2=R is set. The mutual conductance gm of the MOS transistors Q1, Q2 and a resistance value R are set to satisfy the relation of 1/gm≪R. Thus, the drain currents of the MOS transistors Q1, Q2 are obtained by the ratio of an input signal to the resistance value R.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：减少形成在MOS集成电路上的检测电路的增益不均匀性。 解决方案：N沟道MOS晶体管Q1，Q2在源极处连接到电阻器R1，R2。 R1 = R2 = R设定。 MOS晶体管Q1，Q2的电导gm和电阻值R被设定为满足1 / gm？RR的关系。 因此，通过输入信号与电阻值R的比值来获得MOS晶体管Q1，Q2的漏极电流。（C）2005，JPO和NCIPI

    Ring oscillator type voltage controlled oscillator
    35.
    发明专利
    Ring oscillator type voltage controlled oscillator 审中-公开
    振荡器类型电压控制振荡器

    公开(公告)号：JP2005244516A

    公开(公告)日：2005-09-08

    申请号：JP2004050491

    申请日：2004-02-25

    Applicant: Niigata Seimitsu Kk ,  Toyota Industries Corp ,  新潟精密株式会社 ,  株式会社豊田自動織機

    Inventor： IWATA TAIJO ,  MIYAGI HIROSHI

    IPC: H03K3/354 ,  H03K3/03

    Abstract: PROBLEM TO BE SOLVED: To provide a ring oscillator type voltage controlled oscillator of which duty ratio of an output signal is about 50 percentages.
    SOLUTION: Circuit parts 101, 102, 103 being stages of a ring oscillator circuit 100 respectively comprise: variable current sources I1, I2, I3; MOS transistors Q1, Q2, Q3; and bias resistors R1, R2, R3. Capacitors C1, C2, C3 are provided between the circuit parts and charged/discharged by turning ON/OFF of the transistors Q1, Q2, Q3. Further, the circuit configuration of a bias circuit 20 is selected similar to the circuit configuration of the circuit parts 101, 102, 103 being the stages of the ring oscillator circuit 10 to bring the duty ratio of an output signal of the ring oscillator type voltage controlled oscillator to about 50 percentages.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供输出信号的占空比约为50％的环形振荡器型压控振荡器。 解决方案：作为环形振荡器电路100的级的电路部分101,102,103分别包括：可变电流源I1，I2，I3; MOS晶体管Q1，Q2，Q3; 和偏置电阻R1，R2，R3。 电容器C1，C2，C3通过晶体管Q1，Q2，Q3的导通/截止而被提供在电路部件之间并被充电/放电。 此外，偏置电路20的电路配置被选择为类似于作为环形振荡器电路10的级的电路部分101,102,103的电路配置，以使得环形振荡器类型电压的输出信号的占空比 控制振荡器约50％。 版权所有（C）2005，JPO＆NCIPI

    Method of soldering semiconductor part and mounting structure of semiconductor part
    37.
    发明专利
    Method of soldering semiconductor part and mounting structure of semiconductor part 审中-公开
    焊接半导体部分的方法和半导体部分的安装结构

    公开(公告)号：JP2005064206A

    公开(公告)日：2005-03-10

    申请号：JP2003291770

    申请日：2003-08-11

    Applicant: Niigata Seimitsu Kk ,  新潟精密株式会社

    Inventor： MANO AKIHIRO ,  UENO YUKIHIRO ,  URASAWA HIRONORI ,  OISHI YUKI ,  MIYAZAKI SADASHI

    IPC: B23K1/005 ,  H05K1/18 ,  H05K3/34

    CPC classification number: H05K3/3494 ,  B23K1/0056 ,  B23K2201/40 ,  H05K3/3442 ,  H05K2201/10636 ,  H05K2203/081 ,  H05K2203/107 ,  H05K2203/1121 ,  Y02P70/611 ,  Y02P70/613

    Abstract: PROBLEM TO BE SOLVED: To surely solder a semiconductor part on a land which is so small that solder is printed only on the backside of the semiconductor part when the semiconductor part which is not sufficiently heat-resistant and not allowed to be introduced into a reflow furnace is mounted on a circuit board with high mounting density. SOLUTION: The semiconductor part 1 equipped with metal terminals 2 formed on its backside is mounted on a circuit board 5 bringing only the backsides of the metal terminals 2 into contact with cream solders 3, and the sides of the metal terminals 2 are irradiated with a laser beam to heat the backsides of the metal terminals 2 through heat conducted from the backsides of the metal terminals 2, whereby the cream solders 3 coming into contact with the backsides of the metal terminals 2 are melted to solder the metal terminals 2. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了确保将半导体部件焊接在如此小的焊盘上，使得当半导体部件不够耐热且不允许引入时，焊料仅印刷在半导体部件的背面上 进入回流炉安装在具有高安装密度的电路板上。 解决方案：在其背面形成有金属端子2的半导体部件1安装在电路板5上，仅使金属端子2的背面与奶油焊料3接触，金属端子2的侧面 照射激光束，通过从金属端子2的背面传导的热量来加热金属端子2的背面，由此与金属端子2的背面接触的奶油焊料3熔化以焊接金属端子2 （C）2005，JPO＆NCIPI

    Low noise amplifier
    38.
    发明专利
    Low noise amplifier 审中-公开
    低噪音放大器

    公开(公告)号：JP2005006227A

    公开(公告)日：2005-01-06

    申请号：JP2003170106

    申请日：2003-06-13

    Applicant: Niigata Seimitsu Kk ,  Tadahiro Omi ,  Toyota Industries Corp ,  忠弘 大見 ,  新潟精密株式会社 ,  株式会社豊田自動織機

    Inventor： NISHIMUTA TAKESHI ,  MIYAGI HIROSHI ,  OMI TADAHIRO ,  SUGAWA SHIGETOSHI ,  TERAMOTO AKINOBU

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03F1/26 ,  H03G1/00

    CPC classification number: H01L21/82385 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/785 ,  H03F1/26 ,  H03F2200/372 ,  H03G1/0029 ,  H03G1/007

    Abstract: PROBLEM TO BE SOLVED: To provide a low noise amplifier capable of suppressing noise with a small number of components and of amplifying a signal with a high gain, and further to provide a low noise amplifier with a CMOS structure capable of lowering noise and signal distortion.
    SOLUTION: This low noise amplifier has a semiconductor substrate (810A and 810) having at least two crystalline planes and a gate insulating film (820A) formed on the semiconductor substrate to at least two crystalline planes, wherein the channel width of channels respectively formed in the semiconductor substrate along the gate insulating film is shown by the total sum of respective channel width of the channels respectively formed to at least two crystalline planes. The low noise amplifier uses a CMOS transistor (800) obtained by combining a p channel MOS transistor (840A) and an n channel MOS transistor (840B) to suppress noise to a low level, amplifying an input signal.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种能够以少量部件抑制噪声和放大具有高增益的信号的低噪声放大器，并且还提供具有能够降低噪声的CMOS结构的低噪声放大器 和信号失真。 解决方案：该低噪声放大器具有至少具有两个晶体面的半导体衬底（810A和810）和在半导体衬底上形成至少两个结晶面的栅极绝缘膜（820A），其中通道的沟道宽度 分别形成在栅极绝缘膜的半导体衬底中的通道分别表示为分别形成至少两个结晶面的通道的通道宽度的总和。 低噪声放大器使用通过组合p沟道MOS晶体管（840A）和n沟道MOS晶体管（840B）获得的CMOS晶体管（800），以将噪声抑制到低电平，放大输入信号。 版权所有（C）2005，JPO＆NCIPI

    受信機
    40.
    发明专利
    受信機 有权

    公开(公告)号：JPWO2003003595A1

    公开(公告)日：2004-10-21

    申请号：JP2003509653

    申请日：2002-06-24

    Applicant: 新潟精密株式会社

    Inventor： 宮城　弘 ,  弘 宮城

    IPC: H04B1/26 ,  H04B1/28 ,  H04B1/30

    CPC classification number: H04B1/28 ,  H04B1/30

    Abstract: CMOSプロセスあるいはMOSプロセスを用いて半導体基板上に一体成形した場合に発生する低周波ノイズを低減することができる受信機を提供することを目的とする。FM受信機を構成する高周波増幅回路11、混合回路12、局部発振器13、中間周波フィルタ14、16、中間周波増幅器15、リミット回路17、FM検波回路18、ステレオ復調回路19が1チップ部品10として形成されている。この1チップ部品10は、CMOSプロセスあるいはMOSプロセスを用いて半導体基板上に形成されており、混合回路12、中間周波フィルタ14、16、中間周波増幅回路15、局部発振器13に含まれる増幅素子がpチャネル型のFETを用いて形成されている。

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