中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

424 records (took 0.039 seconds)

    METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS
    31.
    发明申请
    METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS 有权
    制造具有非对称嵌入式应变元件的晶体管器件的方法

    公开(公告)号：US20120129311A1

    公开(公告)日：2012-05-24

    申请号：US13355221

    申请日：2012-01-20

    Applicant: Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

    Inventor： Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

    IPC: H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

    Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

    Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

    eFuse macro
    32.
    发明授权
    eFuse macro 有权
    eFuse宏

    公开(公告)号：US08143902B2

    公开(公告)日：2012-03-27

    申请号：US12683101

    申请日：2010-01-06

    Applicant: Rei-Fu Huang ,  Jin-Bin Yang

    Inventor： Rei-Fu Huang ,  Jin-Bin Yang

    IPC: G01R31/07

    CPC classification number: G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An eFuse with at least one fuse unit is provided. The fuse unit includes a common node, a sensing unit with a first input terminal and a second input terminal, at least one fuse coupled between the common node and the first input terminal of the sensing unit with a resistance, and a switching unit coupled between the common node and the second input terminal of the sensing unit. A resistance of the switching unit is equivalent to a first resistance in a normal mode and equivalent to a second resistance in a test mode, and the second resistance is higher than the first resistance. The sensing unit generates an output signal indicating whether the fuse is blown or not according to the resistances of the fuse and the switching unit.

    Abstract translation: 提供至少一个保险丝单元的eFuse。 保险丝单元包括公共节点，具有第一输入端和第二输入端的感测单元，耦合在公共节点与感测单元的第一输入端之间的至少一个熔丝，以及耦合在 传感单元的公共节点和第二输入端。 开关单元的电阻等于在正常模式中的第一电阻并且等于测试模式中的第二电阻，并且第二电阻高于第一电阻。 感测单元根据保险丝和开关单元的电阻产生指示熔丝是否熔断的输出信号。

    DIAPHRAGM AND CONDENSER MICROPHONE USING SAME
    36.
    发明申请
    DIAPHRAGM AND CONDENSER MICROPHONE USING SAME 审中-公开
    使用相同的膜片和冷凝器麦克风

    公开(公告)号：US20110261979A1

    公开(公告)日：2011-10-27

    申请号：US12978577

    申请日：2010-12-26

    Applicant: Bin YANG ,  Rui Zhang

    Inventor： Bin YANG ,  Rui Zhang

    IPC: H04R1/00 ,  G10K13/00

    CPC classification number: H04R19/005 ,  H04R7/04 ,  H04R7/18 ,  H04R2201/003 ,  H04R2307/207 ,  H04R2499/11

    Abstract: A diaphragm is disclosed. The diaphragm includes a vibrating member, a projection extruding from a periphery of the vibrating member, a supporting member surrounding the vibrating member. A first gap is formed between the vibrating member and the supporting member. The supporting member includes a supporting girder surrounding and separated from the projection. A torsion girder is connected to the projection and a fixing girder is parallel to the torsion girder. A second gap is defined between the fixing girder and the torsion girder.

    Abstract translation: 公开了一种隔膜。 隔膜包括振动构件，从振动构件的周边挤出的突起，围绕振动构件的支撑构件。 在振动构件和支撑构件之间形成第一间隙。 支撑构件包括围绕并与突起分离的支撑梁。 扭矩梁连接到突出部，并且固定梁平行于扭矩梁。 在固定梁和扭矩梁之间限定了第二间隙。

    DIAPHRAGM AND SILICON CONDENSER MICROPHONE USING SAME
    37.
    发明申请
    DIAPHRAGM AND SILICON CONDENSER MICROPHONE USING SAME 审中-公开
    使用相同的膜和硅凝胶麦克风

    公开(公告)号：US20110235829A1

    公开(公告)日：2011-09-29

    申请号：US12978574

    申请日：2010-12-26

    Applicant: Bin YANG ,  Rui Zhang

    Inventor： Bin YANG ,  Rui Zhang

    IPC: H04R11/04 ,  H04R7/00

    CPC classification number: H04R19/04

    Abstract: Disclosed is a diaphragm includes a vibrating member, a plurality of supporting members extending from a periphery of the vibrating member along a direction away from a center of the diaphragm, and a plurality of separating portions each located between two adjacent supporting members. Each of the supporting members defines a first beam, a second beam, and at least one slit between the first and second beams.

    Abstract translation: 公开了一种隔膜，包括振动部件，沿着远离振动膜中心的方向从振动部件的周边延伸的多个支撑部件，以及分别设置在两个相邻支撑部件之间的多个分离部。 每个支撑构件限定第一梁，第二梁和在第一和第二梁之间的至少一个狭缝。

    Method for Forming an SOI Schottky Source/Drain Device to Control Encroachment and Delamination of Silicide
    38.
    发明申请
    Method for Forming an SOI Schottky Source/Drain Device to Control Encroachment and Delamination of Silicide 有权
    用于形成SOI肖特基源/排水装置以控制硅化物的侵蚀和分层的方法

    公开(公告)号：US20110230017A1

    公开(公告)日：2011-09-22

    申请号：US12726736

    申请日：2010-03-18

    Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/336

    CPC classification number: H01L29/7839 ,  H01L29/78654

    Abstract: A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A raised semiconductor material is selectively formed on the first semiconductor layer adjacent to the gate structure. The raised semiconductor material is converted into Schottky source and drain regions composed of a metal semiconductor alloy. A non-reacted semiconductor material is present between the Schottky source and drain regions and the dielectric layer.

    Abstract translation: 提供一种制造肖特基场效应晶体管的方法，其包括提供具有覆盖在电介质层上的至少第一半导体层的衬底，其中第一半导体层具有小于10.0nm的厚度。 栅极结构直接形成在第一半导体层上。 凸起的半导体材料选择性地形成在与栅极结构相邻的第一半导体层上。 凸起的半导体材料被转换成由金属半导体合金构成的肖特基源极和漏极区域。 在肖特基源极和漏极区域与电介质层之间存在未反应的半导体材料。

    ETSOI WITH REDUCED EXTENSION RESISTANCE
    39.
    发明申请
    ETSOI WITH REDUCED EXTENSION RESISTANCE 有权
    ETSOI具有降低的延伸电阻

    公开(公告)号：US20110227157A1

    公开(公告)日：2011-09-22

    申请号：US12726889

    申请日：2010-03-18

    Applicant: Bin Yang ,  Man Fai Ng

    Inventor： Bin Yang ,  Man Fai Ng

    IPC: H01L27/12 ,  H01L21/762 ,  H01L29/786

    CPC classification number: H01L29/78618 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

    Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

    Abstract translation: 在诸如极薄的SOI（ETSOI）衬底的SOI衬底上形成半导体，具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层（例如嵌入硅锗（eSiGe））的半导体器件。 实施例包括形成SOI衬底，在SOI衬底上外延形成含硅层，并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后，去除栅电极和下面的含硅层，并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失，从而增加延伸厚度并降低延伸电阻。

Patent Agency Ranking