公开(公告)号：EP1411632A3

公开(公告)日：2005-03-30

申请号：EP03023106.2

申请日：2003-10-10

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co.,Ltd. ,  Hitachi Hybrid network Co., Ltd.

Inventor： Takahashi, Kyoichi, Hitachi ULSI Systems Co. Ltd. ,  Matsudaira, Nobuhiro ,  Akamine, Hitoshi

IPC: H03G3/30

CPC classification number: H03G3/3047 ,  H03F2200/504

Abstract: The present invention provides a high frequency amplifier suitable for use in a wireless communication system which performs detection of an output level necessary for feedback control by a current detection system, wherein control sensitivity in an area low in transmit request level is lowered so that an output level can be controlled over the whole control range with satisfactory accuracy. There is provided a high frequency power amplification electric part constituting a wireless communication system, which performs detection of an output level necessary for feedback control of output power by a current detection system, compares the output level detected signal and an output level designation signal and generates a bias voltage for a high frequency power amplifier according to the difference therebetween to thereby control gain, wherein an nth root converter or a logarithm converter is provided between a current detector and a current-voltage converter.

公开(公告)号：EP2075831A3

公开(公告)日：2010-09-01

申请号：EP08254137.6

申请日：2008-12-23

Applicant: Renesas Technology Corp.

Inventor： Takeuchi, Masahiko , Renesas Technology Corp.

IPC: H01L21/8239 ,  H01L21/8244 ,  H01L27/02 ,  H01L27/105 ,  H01L27/11 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L29/4238

Abstract: Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the sidewall E1. In a planar view, a center line (C2-C2) of a line width D1 in a portion that shared contact holes SC1 and SC2 of gate electrode layers GE1 and GE2 reach is located while shifted with respect to a center line (C1-C1) of a line width D2 in a portion located on channel formation regions CHN1 and CHN2 of gate electrode layers GE1 and GE2. Therefore, a semiconductor device such as an SRAM or TCAM and a photomask that can suppress an opening defect of the shared contact hole are obtained.

公开(公告)号：EP2093661A1

公开(公告)日：2009-08-26

申请号：EP09250343.2

申请日：2009-02-11

Applicant: Renesas Technology Corp.

Inventor： Arakawa, Fumio

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/32

CPC classification number: G06F9/30185 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/3865

Abstract: The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.

公开(公告)号：EP2086005A2

公开(公告)日：2009-08-05

申请号：EP08253677.2

申请日：2008-11-10

Applicant: Renesas Technology Corp.

Inventor： Maeda, Noriaki

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.

Abstract translation: 一种半导体器件包括形成在半导体衬底上并具有相同导电类型的第一MISFET和第二MISFET。 第一MISFET具有布置在半导体衬底上的第一栅极绝缘膜，布置在第一栅极绝缘膜上方的第一栅电极以及第一源极区和第一漏极区。 第二MISFET具有布置在半导体衬底上方的第二栅极绝缘膜，布置在第二栅极绝缘膜上方的第二栅极以及第二源极区和第二漏极区。 第一和第二栅极电耦合，第一和第二源极区电耦合，并且第一和第二漏极区电耦合。 因此，第一和第二MISFET并联连接。 另外，第一和第二MISFET之间的阈值电压不同。

公开(公告)号：EP1248378B1

公开(公告)日：2009-03-11

申请号：EP00900166.0

申请日：2000-01-11

Applicant: Renesas Technology Corp. ,  TTPCOM Limited

Inventor： YAMAWAKI, Taizo, Hitachi Ltd. ,  TANAKA, Satoshi, Hitachi Ltd. ,  KOKUBO, Masaru, Hitachi Ltd. ,  WATANABE, Kazuo, Hitachi Ltd. ,  KASAHARA, Masumi, Hitachi Ltd. ,  HORI, Kazuaki, Hitachi Ltd. ,  HILDERSLEY, Julian, c/o TTPCom Limited

IPC: H04B1/04 ,  H04B1/38 ,  H04L27/12 ,  H03L7/18

CPC classification number: H03C3/0983 ,  H03C3/0925 ,  H03C3/0966 ,  H03D7/163 ,  H03J2200/17 ,  H03L7/23 ,  H04B1/0475 ,  H04B2001/0491 ,  H04L25/03343

Abstract: A transmitter in which the problem of unwanted spurious signals due to harmonics of the output signal from a frequency synthesizer and due to mixture of harmonics of the output signal from a crystal oscillator into a VCO and which facilitates the design of circuits and mounting boards, and a terminal using the transmitter are disclosed. In the transmitter, the relationship between the output frequency of a frequency converting circuit (5) comprising a PLL and the output frequencies of frequency synthesizers (1, 2) is stored. By controlling the output frequencies of the frequency synthesizers inputted to the frequency converting circuit (5) according to the relationship, the unwanted spurious signal is suppressed. Thus, even if an unwanted spurious signal is included in the output of the transmitter because of the crosstalk between circuits and boards, the spurious signal can be suppressed, thereby shortening the time to re-design circuits and boards and reducing the re-designing cost.

公开(公告)号：EP1429227B1

公开(公告)日：2008-02-13

申请号：EP03257713.2

申请日：2003-12-09

Applicant: Renesas Technology Corp.

Inventor： Okuda, Yuichi C/o Renesas Techn. Corp.

IPC: G06F21/06

CPC classification number: H01L23/576 ,  G06K19/073 ,  G06K19/07372 ,  G11C11/412 ,  G11C11/4125 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1418669B1

公开(公告)日：2007-12-05

申请号：EP03023256.5

申请日：2003-10-14

Applicant: Renesas Technology Corp.

Inventor： Irie, Kiyoshi, Renesas Technology Corp. ,  Hori, Kazuaki, Renesas Technology Corp. ,  Hikasa, Kazuhiko, Renesas Technology Corp.

IPC: H03G3/30

CPC classification number: H03G1/0088 ,  H03F3/45098 ,  H03F2200/294 ,  H03F2203/45496 ,  H03F2203/45504 ,  H03F2203/45722 ,  H03G1/0023 ,  H04B1/707 ,  H04B2201/70706

公开(公告)号：EP1722484A3

公开(公告)日：2007-06-06

申请号：EP06017561.9

申请日：2000-11-15

Applicant: Renesas Technology Corp. ,  TTPCOM Limited

Inventor： Tanaka, Satoshi c/o Hitachi, Ltd., IPG ,  Watanabe, Kazuo c/o Hitachi, Ltd., IPG ,  Hotta, Masao c/o Hitachi, Ltd., IPG ,  Hongo,Toyohiko c/o Hitachi, Ltd., IPG ,  Yamawaki, Taizo c/o Hitachi, Ltd., IPG ,  Kasahara, Masumi c/o Hitachi, Ltd., IPG ,  Takikawa, Kumiko c/o Hitachi, Ltd., IPG

IPC: H04B1/30 ,  H03D3/00 ,  H03F1/30

CPC classification number: H04B1/30 ,  H03D2200/0047 ,  H03K21/16

Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers (105, 115, 116, 119, 120, 141) to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers (105, 115, 116) each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider (119, 120, 141) having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier (108) for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit (110) for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Abstract translation: 适合大规模集成的收发器采用直接转换接收来减少滤波器的数量。 而且，通过利用分频器（105,115,116,119,120,141）向RF接收器和发送器提供RF频带上的本地振荡信号，减少了VCO的数量。 每个具有固定分频比的分频器（105,115,116）用于为接收器产生本地振荡信号，而具有可切换分频比的分频器（119,120,141）用于产生本地振荡信号以用于 发射机。 另外，用于基带信号的可变增益放大器（108）配备有用于支持高速数据通信的DC偏移电压检测器和DC偏移消除电路（110），以通过消除滤波器的干预来实现DC偏移的快速消除 在用于抵消抵消的反馈回路内。

公开(公告)号：EP1722484A2

公开(公告)日：2006-11-15

申请号：EP06017561.9

申请日：2000-11-15

Applicant: Renesas Technology Corp. ,  TTPCOM Limited

Inventor： Tanaka, Satoshi c/o Hitachi, Ltd., IPG ,  Watanabe, Kazuo c/o Hitachi, Ltd., IPG ,  Hotta, Masao c/o Hitachi, Ltd., IPG ,  Hongo,Toyohiko c/o Hitachi, Ltd., IPG ,  Yamawaki, Taizo c/o Hitachi, Ltd., IPG ,  Kasahara, Masumi c/o Hitachi, Ltd., IPG ,  Takikawa, Kumiko c/o Hitachi, Ltd., IPG

IPC: H04B1/30

CPC classification number: H04B1/30 ,  H03D2200/0047 ,  H03K21/16

Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers (105, 115, 116, 119, 120, 141) to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers (105, 115, 116) each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider (119, 120, 141) having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier (108) for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit (110) for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Abstract translation: 适合大规模集成的收发器采用直接转换接收，减少滤波器数量。 此外，通过利用分频器（105,115,116,119,120,141）来向RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器（105,115,116）用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器（119,120,141）被用于产生用于接收机的本地振荡信号 发射机。 此外，用于基带信号的可变增益放大器（108）设置有DC偏移电压检测器和DC偏移消除电路（110），用于支持高速数据通信以通过消除滤波器的干扰来实现DC偏移的快速消除 在偏移消除的反馈回路内。

公开(公告)号：EP1115205B1

公开(公告)日：2006-11-15

申请号：EP99943334.5

申请日：1999-09-14

Applicant: Renesas Technology Corp. ,  TTPCOM Limited

Inventor： YAMAWAKI, Taizo, Central Research Laboratory, ,  ENDO, Takefumi, Semiconductor & Integrated ,  WATANABE, Kazuo, Semiconductor & Integrated ,  HORI, Kazuaki, Semiconductor & Integrated ,  HILDERSLEY, Julian, TTP Communications Limited

IPC: H04B1/40 ,  H03L7/08

CPC classification number: H03L7/10 ,  H03D13/007 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/12 ,  H04B1/406

Abstract: A PLL circuit requiring only one LPF is provided to decrease the mounting area and the number of pins and simplify its design, whereas the prior art PLL circuit requires an n number of LPFs. The PLL circuit comprises a variable-gain phase comparator (1), a mixer (2), LPPs (3), n VCOs (4-1 - 4-n), n couplers (5-1 - 5-n), and a control circuit (6) for performing the ON/OFF control of the VCO operation, and the phase difference conversion gain of the variable-gain phase comparator (1) is variable. The control circuit (6) carries out the ON/OFF control of the operation of the VCOs (4-1 - 4-n), and one of the VCOs (4-1 - 4-n) operates depending on a desired operation frequency band, while other VCOs are off. The phase difference conversion gain can be varied depending on the sensitivity of the VCOs (4-1 - 4-n), resulting in the required number of LPFs reduced to one.