公开(公告)号：WO2008015211A1

公开(公告)日：2008-02-07

申请号：PCT/EP2007/057898

申请日：2007-07-31

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  MONDOT, Alexandre ,  MULLER, Markus Gerhard Andreas ,  KORMANN, Thomas

Inventor： MONDOT, Alexandre ,  MULLER, Markus Gerhard Andreas ,  KORMANN, Thomas

IPC: H01L21/20

CPC classification number: H01L21/823814 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823828 ,  H01L27/0922 ,  H01L29/4933 ,  H01L29/4975

Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behaviour according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800 °C, a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract translation: 本发明涉及用于在Si或SiGe表面上选择性沉积Si或SiGe的方法。 该方法根据第一和第二表面区域的掺杂差异，利用物理化学表面行为的差异。 通过提供具有适当浓度范围的硼掺杂的至少一个第一表面区域并且在低于或等于800℃的温度下在预烘烤步骤中将衬底表面暴露于清洁和钝化环境气氛中，随后的沉积步骤 或SiGe不会导致第一表面区域中的层沉积。 该效应用于在不掺杂硼的合适浓度范围内或掺杂有另一种掺杂剂的第二表面区域中选择性沉积Si或SiGe，或不掺杂。 因此，该方法节省了根据现有技术在第二表面区域中选择性沉积Si或SiGe所需的常规光刻序列。

公开(公告)号：WO2007088182A1

公开(公告)日：2007-08-09

申请号：PCT/EP2007/050965

申请日：2007-02-01

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  FREESCALE SEMICONDUCTOR, INC. ,  DUBREUIL, Olivier ,  KORDIC, Srdjan ,  CARAMBERIS, Theodore

Inventor： DUBREUIL, Olivier ,  KORDIC, Srdjan ,  CARAMBERIS, Theodore

IPC: H01L21/00

CPC classification number: H01L21/6708

Abstract: The present invention relates to a cost saving liquid-treatment unit (100). According to the invention, a control unit (152), which is connected to an input port of a control valve (118, 120, 122), is adapted to set, in dependence on the evaporation rate of a treatment liquid on the substrate at the given or desired temperature of the substrate and/or at the given or desired pressure of a gaseous ambient atmosphere at the substrate, a number of dispense pulses to be applied to the substrate for the liquid treatment, a respective pulse duration of individual dispense pulses, and respective dispense-interruption time spans between the individual dispense pulses. This way, the use of treatment liquid is reduced to a minimum amount, thus reducing costs for providing and cleaning treatment liquid.

Abstract translation: 本发明涉及节约成本的液体处理单元（100）。 根据本发明，连接到控制阀（118,120,122）的输入端口的控制单元（152）适于根据基板上处理液体的蒸发速率来设定 衬底的给定或期望温度和/或在衬底上的气体环境气氛的给定或期望压力下，要施加到用于液体处理的衬底的多个分配脉冲，各个分配脉冲的相应脉冲持续时间 ，以及各个分配脉冲之间的分配中断时间跨度。 这样，将处理液的使用降低到最小量，从而降低提供和清洁处理液体的成本。

公开(公告)号：WO2007071674A3

公开(公告)日：2007-06-28

申请号：PCT/EP2006/069910

申请日：2006-12-19

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS CROLLES 2 SAS ,  GOSSET, Laurent ,  ARNAL, Vincent

Inventor： GOSSET, Laurent ,  ARNAL, Vincent

IPC: H01L23/473

Abstract: The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fiuidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fiuidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fiuidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fiuidic- cooling channel segments.

公开(公告)号：WO2011089178A3

公开(公告)日：2011-09-29

申请号：PCT/EP2011050739

申请日：2011-01-20

Applicant: ST MICROELECTRONICS CROLLES 2 ,  CREMER SEBASTIEN ,  LALANNE FREDERIC ,  VERNET MARC

Inventor： CREMER SEBASTIEN ,  LALANNE FREDERIC ,  VERNET MARC

IPC: H01L21/02 ,  G11C11/401 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10882 ,  G11C11/404 ,  G11C11/4094 ,  H01L23/5223 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The integrated circuit comprises a DRAM memory device (DM) comprising at least one memory cell (CEL) including a transistor (TR) having a first electrode (E1), a second electrode (E2) and a control electrode (EC), and a capacitor (CDS) coupled to said first electrode, and at least one electrically conductive line (BLT, BLC) coupled to the second electrode and at least one second electrically conductive line (WL) coupled to the control electrode, said electrically conductive lines (BLT, BLC, WL) being located between the transistor (TR) and the capacitor (CDS). The capacitor can be provided above the fifth metal level.

Abstract translation: 集成电路包括DRAM存储器件（DM），其包括至少一个包括具有第一电极（E1），第二电极（E2）和控制电极（EC））的晶体管（TR）的存储单元（CEL） 耦合到所述第一电极的电容器（CDS）和耦合到所述第二电极的至少一个导电线（BLT，BLC）和耦合到所述控制电极的至少一个第二导电线（WL），所述导电线 ，BLC，WL）位于晶体管（TR）和电容器（CDS）之间。 电容器可以设置在第五金属层上方。

公开(公告)号：WO2008107419A1

公开(公告)日：2008-09-12

申请号：PCT/EP2008/052565

申请日：2008-03-03

Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  TORRES, Joaquin ,  GOSSET, Laurent ,  CHHUN, Sonarith ,  ARNAL, Vincent

Inventor： TORRES, Joaquin ,  GOSSET, Laurent ,  CHHUN, Sonarith ,  ARNAL, Vincent

IPC: H01L21/768 ,  H01L21/321

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76889

Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystalorientations, comprisesselectively incorporating Si into only a first set of crystallites withat least one first crystalorientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier- cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

Abstract translation: 本发明涉及一种在含Cu互连元件上制造扩散阻挡帽的方法，该方法具有至少两种不同晶体取向的晶体，其包括仅将第一组晶体中的Si并入至少一种第一晶体取向中， 条件，并且随后选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，仅在第一组微晶上形成第一屏蔽帽部分，随后选择性地将Si并入仅第二组 的微晶，使用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。 该处理改善了扩散阻挡帽的性质，并确保了互连元件上的扩散阻挡层的连续形成。

公开(公告)号：WO2008074672A1

公开(公告)日：2008-06-26

申请号：PCT/EP2007/063552

申请日：2007-12-07

Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  GOSSET, Laurent Georges ,  TORRES, Joaquin ,  CHHUN, Sonarith

Inventor： GOSSET, Laurent Georges ,  TORRES, Joaquin ,  CHHUN, Sonarith

IPC: H01L21/321 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer (108) of a first dielectric material is deposited on an exposed surface (102.1) of the interconnect element. Susequently, particles (110) are implanted into the first dielectric layer and the interconnect element (102) so as to let the interconnect material mix with the first dielectric material in a first interface region (102.2) between the interconnect element and thefirst dielectric layer.

Abstract translation: 本发明涉及半导体器件的制造方法。 为了改善含铜互连元件和其顶部的扩散阻挡层之间的粘附性，第一介电材料的第一介电层（108）沉积在互连元件的暴露表面（102.1）上。 很显然，将粒子（110）注入到第一介电层和互连元件（102）中，以使互连材料与互连元件和第一介电层之间的第一界面区域（102.2）中的第一介电材料混合。

公开(公告)号：WO2008052940A2

公开(公告)日：2008-05-08

申请号：PCT/EP2007/061537

申请日：2007-10-26

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

Inventor： DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  H01L22/34 ,  H01L2924/3011

Abstract: The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non- defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.

Abstract translation: 本发明涉及一种测试结构，该测试结构包括至少两个被测试器件，它们分别具有处于非缺陷状态的第一电子器件电阻和处于缺陷状态的第二电子器件电阻，第一器件电阻高于第二电气 器件电阻。 在测试结构中，DUT通过第一导电线并联连接到第一测试接触焊盘，并经由第二导线并联连接到第二测试接触焊盘，并且经由相应的第一测试电阻器分别连接到第一导线 其已知各自的电测试电阻，使得第一和第二测试接触焊盘之间的总电阻指示具有第二电气设备电阻的DUT的数量。 测试结构允许在单次测量中并行测试更多的DUT。

公开(公告)号：WO2007129135A1

公开(公告)日：2007-11-15

申请号：PCT/IB2006/001670

申请日：2006-05-05

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ,  ST MICROELECTRONICS (Crolles 2) SAS ,  FREESCALE SEMICONDUCTOR, INC. ,  PAIN, Laurent ,  MANAKLI, Serdar ,  BERVIN, Georges

Inventor： PAIN, Laurent ,  MANAKLI, Serdar ,  BERVIN, Georges

IPC: G03F7/20

CPC classification number: G03F7/70433 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/70383 ,  H01J37/3174 ,  Y10S430/143

Abstract: A method for transferring a predetermined pattern onto a flat support performed by direct writing by means of a particle beam comprises at least: deposition of a photoresist layer on a free surface of the support, application of the beam on exposed areas of the photoresist layer, performing correction by modulation of exposure doses received by each exposed area, developing of the photoresist layer so as to form said pattern. Correction further comprises determination of a substitution pattern (11) comprising at least one subresolution feature and use of the substitution pattern (11) for determining the areas to be exposed when the electron beam is applied. In addition, modulation takes account of the density of the substitution pattern (11) near to each exposed area.

Abstract translation: 通过用粒子束进行直接写入而将预定图案转移到平坦支撑件上的方法至少包括：在支撑体的自由表面上沉积光致抗蚀剂层，在光致抗蚀剂层的曝光区域上施加光束， 通过调制由每个曝光区域接收的曝光剂量来校正光致抗蚀剂层的显影以形成所述图案。 校正还包括确定包含至少一个子分解特征的取代图案（11），并且使用取代图案（11）来确定当施加电子束时要暴露的区域。 此外，调制考虑了靠近每个暴露区域的取代图案（11）的密度。

公开(公告)号：WO2007115954A1

公开(公告)日：2007-10-18

申请号：PCT/EP2007/053106

申请日：2007-03-30

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS CROLLES 2 SAS ,  POUYDEBASQUE, Arnaud ,  CERUTTI, Robin

Inventor： POUYDEBASQUE, Arnaud ,  CERUTTI, Robin

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/785

Abstract: The present invention relates to a CMOS circuit device on a SOI substrate with an oriented silicon surface, comprising on a first substrate region a FET that has a FET channel region of a first conductivity type, and comprising on a second substrate region a FinFET that has a FinFET channel region of a second conductivity type which is opposite to the first conductivity type. The invention also relates to a method for fabricating such a CMOS circuit device. The fabrication of the multi-gate planar FET comprises, at an intermediate step, forming a FET channel stack with an alternating sequence of layers of a FET material and of a sacrificial material and containing main FET -channel faces, which have the same orientation as the oriented silicon surface. According to the invention, a co-integration of multi-gate FET devices is achieved that ensures high carrier mobilities for both NMOS and PMOS FETs.

Abstract translation: 本发明涉及具有取向硅表面的SOI衬底上的CMOS电路器件，在第一衬底区域上包括具有第一导电类型的FET沟道区的FET，并且在第二衬底区域上包括具有 与第一导电类型相反的第二导电类型的FinFET沟道区。 本发明还涉及制造这种CMOS电路器件的方法。 多栅平面FET的制造包括在中间步骤中，形成具有FET材料和牺牲材料的层的交替序列并且包含主FET沟道面的FET沟道堆叠，其具有与 定向硅表面。 根据本发明，实现了多栅极FET器件的共同集成，确保了NMOS和PMOS FET两者的高载流子迁移率。

公开(公告)号：WO2007074111A1

公开(公告)日：2007-07-05

申请号：PCT/EP2006/069911

申请日：2006-12-19

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS CROLLES 2 SAS ,  GOSSET, Laurent ,  ARNAL, Vincent ,  AIMADEDDINE, Mohamed ,  TORRES, Joaquin

Inventor： GOSSET, Laurent ,  ARNAL, Vincent ,  AIMADEDDINE, Mohamed ,  TORRES, Joaquin

IPC: H01L21/768 ,  H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliabilit y in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative configurations of the metal interconnect structure, capping spacers (334) are arranged abutting and covering outer top edges (316c) of interconnect lines (304) or lateral barrier liners (316), respectively. The interconnect structure of the invent ion eliminates the negative influence of these critical regio ns in the metal-interconnect structure on the operational reliability of an integrated-circuit device.

Abstract translation: 本发明涉及用于将集成电路器件中的集成电路元件电连接的金属互连结构。 由于拐角效应和根据现有技术的加工技术制造的互连线的顶部边缘存在的结构缺陷，它解决了镶嵌互连结构中操作可靠性的几个问题。 在金属互连结构的替代配置中，封盖间隔物（334）分别布置成邻接和覆盖互连线（304）或侧向阻挡衬里（316）的外顶边缘（316c）。 本发明的互连结构消除了金属互连结构中的这些关键区域对集成电路器件的操作可靠性的负面影响。