公开(公告)号：WO2005098941A2

公开(公告)日：2005-10-20

申请号：PCT/US2005/010756

申请日：2005-03-30

Applicant: STAKTEK GROUP L.P. ,  CADY, James ,  WILDER, James ,  ROPER, David ,  WEHRLY, JR., Douglas

Inventor： CADY, James ,  WILDER, James ,  ROPER, David ,  WEHRLY, JR., Douglas

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在替代实施例中，形式标准可以包括具有安装支脚的散热器部分。 在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

公开(公告)号：WO2005010990A2

公开(公告)日：2005-02-03

申请号：PCT/US2004/023152

申请日：2004-07-20

Applicant: STAKTEK GROUP, L.P. ,  CADY, James ,  RAPPORT, Russell ,  PARTRIDGE, Julian ,  WEHRLY, James, Jr. ,  WILDER, James ,  ROPER, David ,  BUCHLE, Jeff

Inventor： CADY, James ,  RAPPORT, Russell ,  PARTRIDGE, Julian ,  WEHRLY, James, Jr. ,  WILDER, James ,  ROPER, David ,  BUCHLE, Jeff

IPC: H01L25/10

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. The single memory expansion board is located at the terminus of a transmission line, thus, effectively placing at a relative single point in the addressing system, added memory capacity that would otherwise have required multiple memory expansion boards and, consequently, a longer bus. Therefore, signal degradation issues are mitigated and the system has improved tolerance for higher signal speeds with added memory capacity. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM. Although the present invention is preferably employed to advantage using stacked modules comprised from multiple CSPs, it may be employed with modules comprised from any number and type of integrated circuits including any type of packaging, whether CSP or leaded.

Abstract translation: 通过使用堆叠模块，提供了用于多个集成存储器电路的点对点寻址的系统和方法。 单个存储器扩展板上装有集成电路的堆叠模块。 单个存储器扩展板位于传输线的终点处，因此，有效地放置在寻址系统中的相对单个点处，增加了否则将需要多个存储器扩展板的存储器容量，并且因此需要更长的总线。 因此，信号降级问题得到缓解，并且具有增加的存储容量的系统已经改善了对更高信号速度的容限。 在优选实施例中，不使用堆叠的四个DIMM插槽存储器存取总线被单个DIMM插槽总线替代，该DIMM插槽总线在单个DIMM上支持堆叠高达四个高。 虽然本发明优选地使用由多个CSP组成的堆叠模块，但是可以使用包括任何数量和类型的集成电路的模块，包括任何类型的封装，不管是CSP还是带引线。

公开(公告)号：WO2004109802A1

公开(公告)日：2004-12-16

申请号：PCT/US2003/029000

申请日：2003-09-15

Applicant: STAKTEK GROUP, L.P. ,  RAPPORT, Russell ,  CADY, James, W. ,  WILDER, James ,  ROPER, David, L. ,  WEHRLY, James, Douglas, Jr. ,  BUCHLE, Jeff

Inventor： RAPPORT, Russell ,  CADY, James, W. ,  WILDER, James ,  ROPER, David, L. ,  WEHRLY, James, Douglas, Jr. ,  BUCHLE, Jeff

IPC: H01L25/10

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

公开(公告)号：EP1741134A2

公开(公告)日：2007-01-10

申请号：EP05737564.4

申请日：2005-04-19

Applicant: Staktek Group, L.P.

Inventor： PARTRIDGE, Julian ,  WEHRLY, JR., Douglas

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01327 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.

公开(公告)号：EP1730774A2

公开(公告)日：2006-12-13

申请号：EP05735041.5

申请日：2005-03-30

Applicant: Staktek Group, L.P.

Inventor： CADY, James ,  WILDER, James ,  ROPER, David ,  WEHRLY, JR., Douglas

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/10

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules 10 provided herewith. In a preferred embodiment in accordance with the invention, a form standard 34 provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design 32. In a preferred embodiment, the form standard 34 will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard 34 may include a heat spreader portion 192 with mounting feet 198. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module 10 to reduce the loading effect upon data signals in memory access.

公开(公告)号：WO2008060816A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/081931

申请日：2007-10-19

Applicant: STAKTEK GROUP L.P. ,  SZEWERENKO, Leland ,  GOODWIN, Paul ,  WEHRLY, James, Douglas, JR.

Inventor： SZEWERENKO, Leland ,  GOODWIN, Paul ,  WEHRLY, James, Douglas, JR.

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: The present invention provides a system and method for devising stackable assemblies (70) that may be then stacked to create a stacked circuit module (50). One or more integrated circuit (IC) die (12) are disposed on one or more sides of a redistribution substrate (20) that is preferably flexible circuitry. In some preferred embodiments, the die (12) and redistribution substrate (20) are bonded together and wire-bond (33) connected. Two or more stackable assemblies (70) are interconnected through frame members (30) to create low profile high density stacked circuit modules (50).

Abstract translation: 本发明提供了一种用于设计可堆叠组件（70）的系统和方法，所述可堆叠组件可以被堆叠以产生堆叠的电路模块（50）。 一个或多个集成电路（IC）管芯（12）设置在重新分布衬底（20）的一个或多个侧面上，其优选地是柔性电路。 在一些优选实施例中，将管芯（12）和再分配衬底（20）接合在一起并且引线接合（33）连接。 两个或多个可堆叠组件（70）通过框架构件（30）互连，以形成低轮廓的高密度堆叠电路模块（50）。

公开(公告)号：WO2007136928A2

公开(公告)日：2007-11-29

申请号：PCT/US2007/065009

申请日：2007-03-27

Applicant: STAKTEK GROUP L.P. ,  WEHRLY, Jr., James, Douglas ,  SZEWERENKO, Leland ,  HASKELL, Bert

Inventor： WEHRLY, Jr., James, Douglas ,  SZEWERENKO, Leland ,  HASKELL, Bert

IPC: G06F17/50 ,  H03K19/177 ,  H04N5/335 ,  H03K19/00 ,  H01L25/00 ,  H04N3/14

CPC classification number: G11C5/04 ,  H01L23/13 ,  H01L23/5387 ,  H01L23/5388 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system and method for combining at least two semiconductor die (12, 12FC, 14, 14FC) using multi-layer flex circuitry is provided. A first semiconductor die (12, 12FC) is attached and preferably electrically connected to a first layer of the flex circuitry (20) while a second semiconductor die (14, 14FC) is set, at least in part, into a window (FW) that extends into the flex circuitry (20) to expose a layer of the flex to which the second die (14, 14FC) is attached. When the second semiconductor die (14, 14FC) is a flip-chip device, it is connected through its contacts to the layer of flex exposed in the window and when it is a die with its contact side oriented away from the flex circuitry (20), it is preferably electrically connected with wire bonds to another conductive layer of the flex circuitry (20).

Abstract translation: 提供了一种使用多层柔性电路组合至少两个半导体管芯（12,12FC，14,14FC）的系统和方法。 第一半导体管芯（12,12FC）被附接并且优选地电连接到柔性电路（20）的第一层，而第二半导体管芯（14,14FC）至少部分地被设置到窗口（FW）中， 其延伸到柔性电路（20）中以暴露第二管芯（14,14FC）附接到的柔性层。 当第二半导体管芯（14,14FC）是倒装芯片器件时，其通过其触点连接到暴露在窗口中的柔性层，并且当其是其接触侧定向远离柔性电路（20 ），其优选地与引线键合电连接到柔性电路（20）的另一导电层。

公开(公告)号：WO2007136927A3

公开(公告)日：2007-11-29

申请号：PCT/US2007/065006

申请日：2007-03-27

Applicant: STAKTEK GROUP L.P. ,  WEHRLY, JR., James, Douglas

Inventor： WEHRLY, JR., James, Douglas

IPC: H01L23/02

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure (106) to create an IC-populated structure. In a preferred embodiment, leads (24) of constituent leaded IC packages (20, 22) are configured to allow the lower surface (25) of the leaded IC packages (20, 22) to contact respective surfaces (15, 17) of the flex circuitry structure (106). Contacts for typical embodiments are supported by a rigid portion (120R) of the flex circuitry structure (106) and the IC-populated structure is disposed in a casing (104) to provide card structure for the module.

公开(公告)号：WO2007050120A1

公开(公告)日：2007-05-03

申请号：PCT/US2006/017015

申请日：2006-05-04

Applicant: STAKTEK GROUP L.P. ,  WEHRLY, James, Douglas, JR.

Inventor： WEHRLY, James, Douglas, JR.

IPC: G02B6/12 ,  H05K1/00 ,  H01L23/48

CPC classification number: H01L25/105 ,  H01L21/4871 ,  H01L23/3114 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3511 ,  Y10T29/49169 ,  Y10T29/53209 ,  Y10T29/5327 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module (12, 14) in accordance with a preferred embodiment of the present invention, one or more stiffeners (139) are disposed at least partially between a flex circuit (30, 32) and an integrated circuit. In a two-high stacked circuit module (10) devised in accordance with a preferred embodiment of the present invention, an integrated circuit is stacked above a precursor assembly (105). The two integrated circuits are connected with the flex circuit (130) of the precursor assembly. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules.

Abstract translation: 本发明将集成电路堆叠成节省电路板表面积的模块。 在根据本发明的优选实施例设计的用作堆叠电路模块（12,14）的部件的前体组件中，一个或多个加强件（139）至少部分地设置在柔性电路（30,32） 和集成电路。 在根据本发明的优选实施例设计的两高堆叠电路模块（10）中，集成电路堆叠在前体组件（105）的上方。 两个集成电路与前体组件的柔性电路（130）连接。 本发明可以有益于模块中集成电路的多种配置和组合。

公开(公告)号：WO2006121488A2

公开(公告)日：2006-11-16

申请号：PCT/US2006/007192

申请日：2006-02-28

Applicant: STAKTEK GROUP L.P. ,  WEHRLY, James, Douglas, Jr. ,  WOLFE, Mark ,  GOODWIN, Paul

Inventor： WEHRLY, James, Douglas, Jr. ,  WOLFE, Mark ,  GOODWIN, Paul

IPC: G06F11/00

CPC classification number: H05K1/189 ,  H01L25/0652 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. A rigid substrate is configured to provide space on one side where the populated flex is disposed while in some embodiments, heat management or cooling structures are arranged on one side of the module to mitigate thermal accumulation in the module.

Abstract translation: 灵活的电路填充有沿其主要一侧或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 刚性基板被配置为在其上布置有人造弹性体的一侧上提供空间，而在一些实施例中，热管理或冷却结构布置在模块的一侧以减轻模块中的热积聚。