公开(公告)号：WO2004095458A3

公开(公告)日：2006-05-18

申请号：PCT/US2004011439

申请日：2004-04-14

Applicant: MOTOROLA INC ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

Inventor： GRADISHAR THOMAS L ,  STENGEL ROBERT E

IPC: G06F1/02 ,  G06F1/025 ,  G11C20060101 ,  H03B19/00

CPC classification number: G06F1/025 ,  G06F2211/902

Abstract: A direct digital synthesizer (30) with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer (40) and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter (44) and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal (49) to the quantizer and an output signal (43) from the quantizer. The ROM-less direct digital synthesizer can further include a dither (39) combined at an input of the quantizer.

Abstract translation: 具有噪声整形电路的直接数字合成器（30）可以包括具有量化器（40）的无ROM直接数字合成器和包含量化器的噪声整形环，用于对来自量化器的噪声的量化噪声进行整形。 噪声整形环路可以包括噪声整形滤波器（44），并且噪声整形环路可以将与量化器的输入信号（49）和来自量化器的输出信号（43）之间的差值反馈给噪声整形滤波器。 无ROM直接数字合成器还可以包括在量化器的输入处组合的抖动（39）。

公开(公告)号：WO2004114091A3

公开(公告)日：2004-12-29

申请号：PCT/US2004/019788

申请日：2004-06-18

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

IPC: H03L7/00

Abstract: A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal F ϕ0 from a reference signal F ref A frequency accumulator (132, 152) is preloaded with a preload value P K1 and receives one reference signal cycle as a clock signal, receives a constant K 1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count K MAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value P C1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C 1 as an input thereto. The phase accumulator (136, 156) has a maximum count C MAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal F ref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output F ϕ1 whose phase shift ϕ1 relative to F 0ϕ is a function of P K1 and P C1 .

公开(公告)号：WO2004107579A3

公开(公告)日：2004-12-09

申请号：PCT/US2004/015470

申请日：2004-05-18

Applicant: MOTOROLA, INC., a corporation of the State of Delaware ,  STENGEL, Robert, E.

Inventor： STENGEL, Robert, E.

IPC: H03L7/06

Abstract: A delay locked loop circuit (300) has a delay line (304) with coarse adjustment (322) and fine adjustment (360) inputs. The coarse adjustment input (322) provides an overall adjustment of all of the delay elements while the fine adjustment inputs (360) permit adjusting the individual delay value of each delay element. A first multiplexer (330) produces a first selected output while a second multiplexer (334) produces a second selected output. A measurement circuit (334) measures a difference between the first and second outputs. An error calculator (346) receives the output of the measurement circuit and calculates fine adjustment voltages for each of the selected delay elements. A tuning circuit (350) applies the fine adjustment voltages to the fine adjustment inputs.