公开(公告)号：WO2007104010A3

公开(公告)日：2008-11-27

申请号：PCT/US2007063565

申请日：2007-03-08

Applicant: MOTOROLA INC ,  CAFARO NICHOLAS G ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

Inventor： CAFARO NICHOLAS G ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

IPC: H03L7/08

CPC classification number: H03H11/265 ,  H03K5/131 ,  H03K2005/00065 ,  H03L7/1806

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequenc of the DDS is made variable. Alignment of the edges provided by the DDS delay line (607, 617) may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements (685, 690).

Abstract translation: 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线（607,617）提供的边缘的对准。 通过使用独立的可调延迟元件（685,690）来减少DDS延迟线中的不匹配误差。

公开(公告)号：WO2006052416A3

公开(公告)日：2006-08-31

申请号：PCT/US2005037858

申请日：2005-10-21

Applicant: MOTOROLA INC ,  CAFARO NICHOLAS G ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

Inventor： CAFARO NICHOLAS G ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

IPC: H04L7/00

CPC classification number: H04L7/0083 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00286 ,  H03L7/0812 ,  H04L7/0337

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract translation: DPC（300）包括：用于产生时钟信号的频率源（310）; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于生成包括顺序逻辑设备（500,510,520）和组合网络的输出信号的加窗选择电路。 一种在DPC中使用的方法包括：基于识别延迟线上的第一输出抽头的期望输出信号接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头以接收至少两个不同的相移时钟信号; 以及基于所述控制信号和所接收的基本上是所需输出信号的相移时钟信号来产生（420）输出信号。

公开(公告)号：WO2004095458A3

公开(公告)日：2006-05-18

申请号：PCT/US2004011439

申请日：2004-04-14

Applicant: MOTOROLA INC ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

Inventor： GRADISHAR THOMAS L ,  STENGEL ROBERT E

IPC: G06F1/02 ,  G06F1/025 ,  G11C20060101 ,  H03B19/00

CPC classification number: G06F1/025 ,  G06F2211/902

Abstract: A direct digital synthesizer (30) with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer (40) and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter (44) and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal (49) to the quantizer and an output signal (43) from the quantizer. The ROM-less direct digital synthesizer can further include a dither (39) combined at an input of the quantizer.

Abstract translation: 具有噪声整形电路的直接数字合成器（30）可以包括具有量化器（40）的无ROM直接数字合成器和包含量化器的噪声整形环，用于对来自量化器的噪声的量化噪声进行整形。 噪声整形环路可以包括噪声整形滤波器（44），并且噪声整形环路可以将与量化器的输入信号（49）和来自量化器的输出信号（43）之间的差值反馈给噪声整形滤波器。 无ROM直接数字合成器还可以包括在量化器的输入处组合的抖动（39）。

公开(公告)号：WO2007061523A3

公开(公告)日：2007-09-13

申请号：PCT/US2006039626

申请日：2006-10-09

Applicant: MOTOROLA INC ,  THOMPSON BRUCE M ,  OOI LENG H ,  STENGEL ROBERT E

Inventor： THOMPSON BRUCE M ,  OOI LENG H ,  STENGEL ROBERT E

IPC: G06F15/00

CPC classification number: H04B1/0475

Abstract: A vector signal processor (80) can include a digital to time converter (DTC), an RF memory (RFM) or an electronically tunable transmission line (ETTL) (82), a mixer, or other phase shifter (70) for receiving an output of the DTC or the ETTL, and a controller for selectively controlling the harmonic processing of the DTC, RFM or the ETTL and the phase processing of the mixer. The vector signal processor can uncouple a relative phase of a fundamental signal with respect to harmonics of the fundamental signal. The vector signal processor uses selective phase processing of the fundamental signal and related harmonic components. In a specific embodiment, the vector signal processor cancels harmonics of the fundamental signal and more specifically can cancel a third harmonic of the fundamental signal.

Abstract translation: 矢量信号处理器（80）可以包括数字到时间转换器（DTC），RF存储器（RFM）或电子可调谐传输线（ETTL）（82），混频器或其它移相器（70） DTC或ETTL的输出，以及用于选择性地控制DTC，RFM或ETTL的谐波处理和混频器的相位处理的控制器。 矢量信号处理器可以分离基本信号相对于基波信号的谐波的相对相位。 矢量信号处理器使用基本信号和相关谐波分量的选择性相位处理。 在具体实施例中，矢量信号处理器消除基波信号的谐波，更具体地可以消除基波信号的三次谐波。

公开(公告)号：WO2005109647A3

公开(公告)日：2008-09-12

申请号：PCT/US2005008549

申请日：2005-03-14

Applicant: MOTOROLA INC ,  WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO JR MANUEL P ,  GAILUS PAUL H ,  STENGEL ROBERT E

Inventor： WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO MANUEL P JR ,  GAILUS PAUL H ,  STENGEL ROBERT E

IPC: H03L7/06 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081 ,  H03L7/16

CPC classification number: H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0812

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Abstract translation: 延迟锁定环路300，其包括：用于产生具有可调频率的时钟信号（322）的可调频率源（320） 调整和抽头选择控制器（310），用于根据第二频率确定第一频率，并使频率源将时钟信号的频率调整到基本上第一频率;第二频率是期望的频率 第一输出信号; 延迟线（330），被配置为接收用于产生多个相移时钟信号的时钟信号; 以及第一选择电路（370），用于接收多个相移时钟信号，并用于在调整和抽头选择控制器的控制下一次一个地选择第一个相移时钟信号序列，用于产生 第一输出信号具有基本上第二频率。

公开(公告)号：WO2004095191A3

公开(公告)日：2005-03-03

申请号：PCT/US2004012139

申请日：2004-04-20

Applicant: MOTOROLA INC ,  TOMERLIN ANDREW ,  CAFARO NICHOLAS GIOVANNI ,  STENGEL ROBERT E

Inventor： TOMERLIN ANDREW ,  CAFARO NICHOLAS GIOVANNI ,  STENGEL ROBERT E

IPC: G06F1/08 ,  G06F15/78 ,  G06F1/04

CPC classification number: G06F15/7867 ,  G06F1/08 ,  Y02D10/12 ,  Y02D10/13

Abstract: A reconfigurable processor circuit (200) consistent with certain embodiments of the present invention has an array of configurable circuit blocks, wherein certain of the configurable circuit blocks comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor (218) configures a function of a plurality of the configurable circuit blocks. A memory (224) stores program instructions used by the control processor (218). A multiple frequency generator (212) receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (218). A timing control circuit (236) receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit (236) operates under control of the control processor (218).

Abstract translation: 与本发明的某些实施例一致的可重构处理器电路（200）具有可配置电路块的阵列，其中某些可配置电路块包括可配置的算术逻辑单元和时钟数字逻辑电路之一。 控制处理器（218）配置多个可配置电路块的功能。 存储器（224）存储由控制处理器（218）使用的程序指令。 多频发生器（212）接收参考时钟并从其合成多个时钟信号，每个时钟信号由控制处理器（218）频率配置。 定时控制电路（236）接收多个时钟信号，在多个电路块中分配不同频率的多个时钟信号，并将时钟信号发送到电路块，其中定时控制电路（236）在控制下工作 的控制处理器（218）。

公开(公告)号：WO2004107579A2

公开(公告)日：2004-12-09

申请号：PCT/US2004015470

申请日：2004-05-18

Applicant: MOTOROLA INC ,  STENGEL ROBERT E

Inventor： STENGEL ROBERT E

IPC: H03L7/081 ,  H03L7/087 ,  H03L

CPC classification number: H03L7/087 ,  H03L7/0814 ,  H03L7/0818

Abstract: A delay locked loop circuit 300 consistent with certain embodiments of the present invention has a delay line 304 with coarse adjustment 322 and fine adjustment 360 inputs. The coarse adjustment input 322 provides an overall adjustment of all of the delay line's delay elements while the fine adjustment inputs 360 permit adjusting the individual delay value of each delay element. A first multiplexer 330 receives the delay tap outputs and produces a first selected output while a second multiplexer 334 also receives the delay tap outputs and produces a second selected output. A measurement circuit 344 measures a difference between the first and second output as a measurement of a selected delay element's delay value. An error calculator 346 receives the output of the measurement circuit and calculates fine adjustment voltages for each of the selected delay elements. A tuning circuit 350 applies the fine adjustment voltages to the fine adjustment inputs of the delay line 304.

Abstract translation: 与本发明的某些实施例一致的延迟锁定环电路300具有粗略调整322和微调360输入的延迟线304。 粗调输入322提供所有延迟线的延迟元件的总体调整，而微调输入360允许调整每个延迟元件的各个延迟值。 第一多路复用器330接收延迟抽头输出并产生第一选择输出，而第二多路复用器334还接收延迟抽头输出并产生第二选择的输出。 测量电路344测量第一和第二输出之间的差作为所选择的延迟元件的延迟值的测量值。 误差计算器346接收测量电路的输出，并计算每个所选择的延迟元件的微调电压。 调谐电路350将微调电压施加到延迟线304的微调输入端。

公开(公告)号：WO2009018199A3

公开(公告)日：2010-04-08

申请号：PCT/US2008071312

申请日：2008-07-28

Applicant: MOTOROLA INC ,  NAGARAJ GEETHA B ,  CAFARO NICHOLAS G ,  HEKMANN RALF ,  STENGEL ROBERT E ,  MILLER SCOTT

Inventor： NAGARAJ GEETHA B ,  CAFARO NICHOLAS G ,  HEKMANN RALF ,  STENGEL ROBERT E ,  MILLER SCOTT

IPC: H03L7/081

CPC classification number: H03B21/02 ,  H03L7/0814

Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Abstract translation: 提供了一种用于管理数字到时间转换（DTC）的方法和系统。 该方法包括接收第一射频（RF）信号和第二RF信号。 第二RF信号是相移的第一RF信号。 该方法还包括将第一RF信号转换为第一中频（IF）信号，将第二RF信号转换为第二IF信号。 此外，基于时差测量技术来估计第一IF信号和第二IF信号之间的时间延迟。 基于估计的时间延迟来处理第二RF信号以补偿与第二RF信号相关联的延迟误差。

公开(公告)号：WO2008042550A4

公开(公告)日：2009-01-08

申请号：PCT/US2007077819

申请日：2007-09-07

Applicant: MOTOROLA INC ,  THOMPSON BRUCE M ,  STENGEL ROBERT E

Inventor： THOMPSON BRUCE M ,  STENGEL ROBERT E

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F1/565 ,  H03F3/26 ,  H03F3/602 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/45394 ,  H03F2203/45731

Abstract: An apparatus and method for eliminating unwanted signal power dissipation in balanced amplifier circuits and for prohibiting unwanted signal power from appearing at the balanced amplifier load is presented. Load impedances to the amplifier power output transistors are maintained very low at unwanted frequencies, and are at an operational impedance level at the fundamental frequency. An impedance network control concept is presented, which may be either manually or automatically implemented.

Abstract translation: 提出了用于消除平衡放大器电路中不需要的信号功率耗散并且用于禁止在平衡放大器负载处出现不想要的信号功率的装置和方法。 放大器功率输出晶体管的负载阻抗在不需要的频率下保持非常低，并且在基频处于工作阻抗级。 提出了阻抗网络控制概念，可以手动或自动实现。

公开(公告)号：WO2007143255B1

公开(公告)日：2008-09-18

申请号：PCT/US2007065030

申请日：2007-03-27

Applicant: MOTOROLA INC ,  STENGEL ROBERT E

Inventor： STENGEL ROBERT E

IPC: G06F1/02

CPC classification number: G06F1/025 ,  H03K5/131 ,  H03K2005/00045

Abstract: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

Abstract translation: 与本发明的某些实施例一致的信号发生器具有产生周期性的参考时钟输出脉冲序列的参考时钟（34）。 窗口产生器（38）产生多个时间窗口，所选择的多个参考时钟输出脉冲通过该时间窗口被选择性地作为窗口脉冲通过，使得窗口脉冲形成选定的脉冲图案。 可编程延迟（46）具有延迟分辨率，其延迟时间比时钟输出脉冲的周期更精细。 可编程延迟（46）将每个加窗脉冲延迟编程的延迟时间，从而为加窗脉冲提供定时校正以产生脉冲的输出模式。