公开(公告)号：US20230133912A1

公开(公告)日：2023-05-04

申请号：US17515212

申请日：2021-10-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant ,  Misaele Marletti ,  Alessandro Daolio

IPC: G01R31/317 ,  G01R31/319 ,  G01R31/28

Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.

公开(公告)号：US20230065623A1

公开(公告)日：2023-03-02

申请号：US17815807

申请日：2022-07-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Roberto Colombo

IPC: G11C29/42 ,  G11C29/36 ,  G11C29/48

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

公开(公告)号：US20230053798A1

公开(公告)日：2023-02-23

申请号：US17819749

申请日：2022-08-15

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/28 ,  G06F9/30

Abstract: A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.

公开(公告)号：US11526458B2

公开(公告)日：2022-12-13

申请号：US17245894

申请日：2021-04-30

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Fred Rennig ,  Vaclav Dvorak ,  Ludek Beran

IPC: G06F13/362 ,  G06F11/07 ,  H04L12/40 ,  H04L7/00 ,  H04L5/00 ,  G06F13/42 ,  H04L43/55

Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.

公开(公告)号：US20220382695A1

公开(公告)日：2022-12-01

申请号：US17747800

申请日：2022-05-18

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger ,  Roberto Colombo

IPC: G06F13/28 ,  G06F13/42 ,  G06F9/30 ,  G06F9/38 ,  G06F21/60 ,  G06F21/72

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

公开(公告)号：US20220334862A1

公开(公告)日：2022-10-20

申请号：US17235206

申请日：2021-04-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Deepak BARANWAL ,  Amritanshu ANAND ,  Roberto COLOMBO ,  Boris VITTORELLI

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/48

Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.

公开(公告)号：US20220308892A1

公开(公告)日：2022-09-29

申请号：US17654537

申请日：2022-03-11

Applicant: STMicroelectronics S.r.i ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Rene Grossier ,  Fabio Enrico Carlo Disegni

IPC: G06F9/4401 ,  G06F9/30

Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

公开(公告)号：US20220159807A1

公开(公告)日：2022-05-19

申请号：US17523641

申请日：2021-11-10

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application S.R.O.

Inventor： Donato TAGLIAVIA ,  Vincenzo POLISI ,  Calogero Andrea TRECARICHI ,  Francesco Nino MAMMOLITI ,  Jochen BARTHEL ,  Ludek BERAN

IPC: H05B45/46 ,  H05B45/38

Abstract: A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.

公开(公告)号：US20220137128A1

公开(公告)日：2022-05-05

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar GOYAL ,  Deepak BARANWAL ,  Thomas SZURMANT ,  Nicolas Bernard GROSSIER

IPC: G01R31/317 ,  G01R31/3185

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

公开(公告)号：US20220018907A1

公开(公告)日：2022-01-20

申请号：US17368198

申请日：2021-07-06

Applicant: STMicroelectronics Application GMBH

Inventor： Markus Ekler

IPC: G01R31/382 ,  G01R31/396 ,  G01R31/367 ,  B60L58/12 ,  H01M10/42

Abstract: An embodiment processing system comprises terminals configured to be connected to cells of a rechargeable battery to receive cell voltages, a digital processing circuit, a serial communication interface and a transmission queue interfacing the digital processing circuit with the serial communication interface for parallel operation. The digital processing circuit synchronously acquires a given number of digital samples of each of the cell voltages and stores them to a memory. The digital processing circuit encodes the digital samples stored to the memory via a data compression module, and stores the encoded data to the transmission queue. For example, the data compression module may generate the encoded data by subtracting a given offset from each digital sample to generate values indicative of the dynamic variation of each sample with respect to the offset, and removing a given number of most significant bits from each value.