公开(公告)号：EP3378159A1

公开(公告)日：2018-09-26

申请号：EP16867015.6

申请日：2016-11-16

Applicant: Tensorcom, Inc.

Inventor： SOE, Zaw ,  JING, Kevin ,  GAO, Steve

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

CPC classification number: H03G1/007 ,  H03F3/45197 ,  H03F2200/165 ,  H03F2200/69 ,  H03F2203/45372 ,  H03F2203/45374 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03G5/28 ,  H03H11/1286

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：EP2575603A4

公开(公告)日：2014-03-26

申请号：EP11790368

申请日：2011-06-01

Applicant: TENSORCOM INC

Inventor： LAKKIS ISMAIL ,  LAW HOCK

IPC: A61B5/01 ,  A61B5/00 ,  A61B5/0444 ,  G06Q50/00 ,  H04B7/24 ,  H04W52/02 ,  H04W76/04

CPC classification number: H04W56/0015 ,  A61B5/00 ,  A61B5/0002 ,  A61B5/002 ,  A61B5/0022 ,  A61B5/0024 ,  A61B5/0026 ,  A61B5/0028 ,  A61B5/0059 ,  A61B5/01 ,  A61B5/02028 ,  A61B5/0205 ,  A61B5/02055 ,  A61B5/021 ,  A61B5/02438 ,  A61B5/0507 ,  A61B5/0816 ,  A61B5/11 ,  A61B5/4362 ,  A61B5/6833

公开(公告)号：WO2014025713A1

公开(公告)日：2014-02-13

申请号：PCT/US2013/053680

申请日：2013-08-06

Applicant: TENSORCOM, INC.

Inventor： CHEN, Jiashu

IPC: H04L7/00

CPC classification number: G06F1/10 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H04B7/0617 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/22 ,  Y02D70/444

Abstract: Herein is a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (~600 μm) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.

Abstract translation: 这里是用于波束形成系统的低功率裸片60GHz分配网络，其可随着发射机数量的增加而缩放。 如果使用传输线形成，尺寸将与四分之一波长（〜600μm）成比例的传输线路功率分配器和正交混合器由电感器/电容器构成，并将面积减少80％以上。 输入同相I时钟和输入正交Q时钟被组合成锁定同相I时钟和正交Q时钟之间的相位关系的单个复合时钟波形。 复合时钟通过使用耦合在晶片表面上的源和目的位置的共平面波导（CPW）形成的单个传输线传输。 一旦个体需要同相I和正交Q时钟，它们可以从复合时钟波形在目的地产生。

公开(公告)号：WO2014015011A1

公开(公告)日：2014-01-23

申请号：PCT/US2013/050842

申请日：2013-07-17

Applicant: TENSORCOM, INC.

Inventor： YANG, HungYu ,  BALBIEN, Joel ,  GABARA, Thaddeus

IPC: H01Q21/10 ,  H01Q21/08

CPC classification number: H01Q1/007 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/521

Abstract: A portable unit with an endfire antenna and operating at 60 GHz makes an optimum communication channel with an endfire antenna in an array of antennas distributed over the area of a ceiling. The portable unit is pointed towards the ceiling and the system controlling the ceiling units selects and adjusts the positioning of an endfire antenna mounted on a 3-D adjustable rotatable unit. Several transceivers can be mounted together, offset from one another, to provide a wide coverage in both azimuth direction and elevation direction. These units can be rigidly mounted as an array in a ceiling apparatus. The system controlling the ceiling array selects one of the transceivers in one of the units to make the optimum communication channel to the portable unit. The system includes the integration of power management features by switching between Wi-Fi in favor of the 60 GHz channel.

Abstract translation: 具有端射天线并以60GHz操作的便携式单元与分布在天花板区域上的天线阵列中的端射天线形成最佳通信信道。 便携式设备被指向天花板，并且控制天花板单元的系统选择并调节安装在3-D可调节可旋转单元上的端面天线的定位。 几个收发器可以一起安装在一起，彼此偏移，以便在方位方向和仰角方向上提供广泛的覆盖。 这些单元可以作为阵列刚性地安装在天花板装置中。 控制天花板阵列的系统选择其中一个单元中的一个收发器，以将便携式单元的最佳通信信道。 该系统包括通过在支持60 GHz频道的Wi-Fi之间切换来集成电源管理功能。

公开(公告)号：WO2013154847A1

公开(公告)日：2013-10-17

申请号：PCT/US2013/034728

申请日：2013-03-30

Applicant: TENSORCOM, INC.

Inventor： LAKKIS, Ismail

IPC: H04L25/10 ,  H04L25/03

CPC classification number: H04B1/525 ,  H04B1/123 ,  H04B1/30

Abstract: Transceiver calibration is a critical issue for proper transceiver operation. The transceiver comprises at least one RF transmit chain and one RF receive chain. A closed loop path is formed from the digital block, the RF transmit chain, the substrate coupling, the RF receive chain back to the digital block and is used to estimate and calibrate the transceiver parameters over the operating range of frequencies. The substrate coupling eliminates the need for the additional circuitry saving area, power, and performance. In place of the additional circuitry, the digital block which performs baseband operations can be reconfigured into a software or/and hardware mode to calibrate the transceiver. The digital block comprises a processor and memory and is coupled to the front end of the RF transmit chain and the tail end of the RF receive chain.

Abstract translation: 收发器校准是正确的收发器操作的关键问题。 收发器包括至少一个RF发射链和一个RF接收链。 从数字模块，RF发射链，衬底耦合，RF接收链回到数字模块形成闭环路径，并用于在频率的工作范围内估计和校准收发器参数。 基板耦合消除了额外的电路节省面积，功率和性能的需要。 代替附加电路，执行基带操作的数字模块可以重新配置成软件或/和硬件模式，以校准收发器。 数字模块包括处理器和存储器，并且耦合到RF发射链的前端和RF接收链的尾端。

公开(公告)号：WO2013102159A1

公开(公告)日：2013-07-04

申请号：PCT/US2012/072215

申请日：2012-12-29

Applicant: TENSORCOM, INC.

Inventor： REHMAN, Syed

IPC: H03L7/099 ,  H03B5/08

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0062 ,  H03L7/18

Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.

Abstract translation: RCL谐振电路中的电容调整通常通过调整施加到电容器一侧的直流电压来进行。 电容器的一侧通常连接到RCL谐振电路中的再生电路的输出节点或栅极。 谐振电路的电容成为由谐振电路产生的直流电压和交流正弦信号的函数。 通过电容耦合电容器的两个节点，DC电压可以在输出波形的全摆幅时控制电容器的值。 此外，代替RCL谐振电路驱动负载输出的单个差分功能，每个输出驱动独立的单端功能; 从而提供两个同时的操作来代替一个差分功能。

公开(公告)号：WO2013043954A4

公开(公告)日：2013-07-04

申请号：PCT/US2012056463

申请日：2012-09-21

Applicant: TENSORCOM INC

Inventor： SOE ZAW

IPC: H03L7/06

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供了在60 GHz工作的压控振荡器设计。 其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。 虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。 提出了使用几种技术的除以2。 前馈，时钟放大和串联峰值电感，以克服这些限制。

公开(公告)号：WO2013085966A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/067898

申请日：2012-12-05

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw

IPC: H04B1/16 ,  H03D7/00

CPC classification number: H03D7/1441 ,  H03D7/1466 ,  H03F1/223 ,  H03F3/193

Abstract: A cascode common source and common gate LNAs operating at 60GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

Abstract translation: 引入并描述了以60GHz工作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：US10734957B2

公开(公告)日：2020-08-04

申请号：US16352575

申请日：2019-03-13

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Kevin Jing ,  Steve Gao

IPC: H03G5/28 ,  H03H11/12 ,  H03G1/00 ,  H03F3/45

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：US10277182B2

公开(公告)日：2019-04-30

申请号：US15833458

申请日：2017-12-06

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Kevin Jing ,  Steve Gao

IPC: H03G1/00 ,  H03H11/12 ,  H03F3/45 ,  H03G5/28

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.