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公开(公告)号：KR1020090116978A
公开(公告)日：2009-11-12
申请号：KR1020080042819
申请日：2008-05-08
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: PURPOSE: A multilayer chip capacitor is provided to secure a stable electrical connection between a lead and an external electrode by more increasing a width of a connecting part between the external electrode and the lead than a width of a connecting part between a main electrode part and the lead. CONSTITUTION: A multilayer chip capacitor includes a main body, a plurality of internal electrodes(21), and a plurality of external electrodes(31). The main body is formed by laminating a plurality of dielectric layers(10). The internal electrodes are arranged inside the main body. The external electrodes are arranged in an outer surface of the main body. Each external electrode is connected to the internal electrode. Each internal electrode has a main electrode part(21m) and one or more leads(21a). The lead is drawn from the main electrode part to a side surface of the main body, and is connected to the external electrode.
Abstract translation: 目的：提供一种多层片状电容器，通过使外部电极和引线之间的连接部分的宽度比主电极部分和引线的连接部分的宽度更大地增加引线和外部电极之间的稳定的电连接， 带头。 构成：多层片状电容器包括主体，多个内部电极（21）和多个外部电极（31）。 主体通过层叠多个电介质层（10）而形成。 内部电极配置在主体的内部。 外部电极布置在主体的外表面中。 每个外部电极连接到内部电极。 每个内部电极具有主电极部分（21m）和一个或多个引线（21a）。 引线从主电极部分被拉伸到主体的侧表面，并且连接到外部电极。
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公开(公告)号：KR1020090095999A
公开(公告)日：2009-09-10
申请号：KR1020080021310
申请日：2008-03-07
Applicant: 삼성전기주식회사
Abstract: A multilayer chip capacitor is provided to increase ESR(Equivalent Series Resistance) by increasing a length of a current path formed by an inner electrode of different polarity. A capacitor main body is formed by laminating a plurality of dielectric layers. The capacitor main body has a first side, a second side, a first end surface, and a second end surface. Outer electrodes(131~138) of different polarity are arranged in the first side and the second side of the capacitor main body by turns. Inner electrodes(121~128) of different polarity are arranged inside the capacitor main body by turns. Each inner electrode one or more leads(121a~128a). The lead is connected to the outer electrode. A horizontal distance between the leads of the inner electrodes is larger than a pitch between the outer electrodes.
Abstract translation: 提供多层片状电容器，通过增加由不同极性的内部电极形成的电流路径的长度来增加ESR（等效串联电阻）。 电容器主体通过层叠多个电介质层而形成。 电容器主体具有第一面，第二面，第一端面和第二端面。 不同极性的外电极（131〜138）轮流布置在电容器主体的第一侧和第二侧。 不同极性的内电极（121〜128）轮流布置在电容器主体的内部。 每个内电极一个或多个引线（121a〜128a）。 引线连接到外电极。 内部电极的引线之间的水平距离大于外部电极之间的间距。
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公开(公告)号：KR1020090090491A
公开(公告)日：2009-08-26
申请号：KR1020080015732
申请日：2008-02-21
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: A stack chip capacitor is provided to improve connection between an internal electrode and an external electrode by drawing out the lead of the internal electrode to the corner of the chip. A capacitor body has first and second long sides(Lf1,Lf2) and first and second short sides(Sf1,Sf2). The first and second outer electrodes(111,112) are arranged in the first and second long sides. The first and second outer electrodes have the different polarity. The first inner electrode pair has a first inner electrode(A1) and a second inner electrode(B1). The second inner electrode pair has a third inner electrode(C1) and a fourth inner electrode(D1). The first lead of the first inner electrode is connected to the first outer electrode. The second lead of the second inner electrode is connected to the second outer electrode. The third lead of the third inner electrode is connected to the first outer electrode. The fourth lead of the fourth inner electrode is connected to the second outer electrode.
Abstract translation: 通过将内部电极的引线拉出到芯片的角部来提供堆叠片状电容器来改善内部电极和外部电极之间的连接。 电容器本体具有第一和第二长边（Lf1，Lf2）和第一和第二短边（Sf1，Sf2）。 第一和第二外部电极（111,112）布置在第一和第二长边。 第一和第二外部电极具有不同的极性。 第一内电极对具有第一内电极（A1）和第二内电极（B1）。 第二内电极对具有第三内电极（C1）和第四内电极（D1）。 第一内部电极的第一引线连接到第一外部电极。 第二内部电极的第二引线连接到第二外部电极。 第三内部电极的第三引线连接到第一外部电极。 第四内部电极的第四引线连接到第二外部电极。
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公开(公告)号：KR100900673B1
公开(公告)日：2009-06-01
申请号：KR1020070009913
申请日：2007-01-31
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: 본 발명은, 복수의 유전체층이 적층되어 형성되며, 직육면체 형상을 갖는 커패시터 본체; 상기 커패시터 본체의 대향하는 2개 장측면(longer side faces)의 각각에 서로 교대로 배열되며, 서로 다른 극성을 갖고 서로 마주보도록 배치된 적어도 3쌍의 제 1외부전극 및 제2 외부전극; 및 상기 커패시터 본체 내에서 상기 유전체층에 의해 분리되어 서로 교대로 배치되며, 리드를 통해 상기 제1 및 제2 외부전극에 각각 연결되는 복수의 제1 내부 전극 및 제2 내부 전극을 포함하며, 상기 커패시터 본체의 길이(L:length)가 폭(W:width)의 2.5배 이상인 적층형 칩 커패시터를 제공한다.
적층형 칩 커패시터, 적층 콘덴서, 외부 전극-
公开(公告)号：KR1020090026174A
公开(公告)日：2009-03-11
申请号：KR1020090012364
申请日：2009-02-16
Applicant: 삼성전기주식회사
Abstract: A multilayer chip capacitor is provided to steadily supply the power to the radio-frequency circuit by preventing the degradation of excessive ESR. A four terminal capacitor comprises a capacitor main body made of a plurality of dielectric layers(1000); the first and fourth outer electrodes of the different kind polarity formed in the lower-part of the main body. The outer electrode is by turns arranged in the lower-part(A) of the main body. Inner electrodes are perpendicularly arranged in the lower-part of the main body. The inner electrode has one lead which is drawn to the lower-part. One block is formed by the inner electrode. The lead(1010a) of the first inner electrode(1010) is connected to the first outer portion electrode(131). The lead(1020a) of the second inner electrode(1020) is connected to the second outer electrode(132). The lead(1030a) of the third inner electrode(1030) is connected to the third outer electrode(133). The lead(1040a) of the fourth inner electrode(1040) is connected to the fourth outer electrode(134).
Abstract translation: 提供了一种多层片状电容器，通过防止过度ESR的劣化来稳定地向射频电路供电。 四端电容器包括由多个电介质层（1000）制成的电容器主体; 形成在主体的下部的不同种类的极性的第一和第四外部电极。 外电极依次布置在主体的下部（A）中。 内电极垂直设置在主体的下部。 内部电极具有一个引线，其被吸引到下部。 一块由内电极形成。 第一内部电极（1010）的引线（1010a）与第一外部电极（131）连接。 第二内部电极（1020）的引线（1020a）连接到第二外部电极（132）。 第三内部电极（1030）的引线（1030a）连接到第三外部电极（133）。 第四内部电极（1040）的引线（1040a）连接到第四外部电极（134）。
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Patent Agency Ranking
公开(公告)号：KR100856242B1
公开(公告)日：2008-09-03
申请号：KR1020060034399
申请日：2006-04-17
Applicant: 삼성전기주식회사
Abstract: 본 발명은 초고용량 캐패시터 및 그 제조방법에 관한 것이다.
본 발명의 초고용량 캐패시터는, 유전체층; 상기 유전체층 사이에 교대로 배열된 적어도 하나의 제 1내부전극층 및 제 2내부전극층; 상기 제 1내부전극층중 적어도 하나와 전기적으로 연결된 제 1외부전극; 및 상기 제 2내부전극층중 적어도 하나와 전기적으로 연결된 제 2외부전극;을 포함하고,
상기 제 1내부전극층 및 제 2내부전극층은 각각 그 층에 실질적으로 수직하는 다수의 수직전극을 가지며, 상기 제 1내부전극층의 수직전극과 상기 제 2내부전극층의 수직전극이 상호 교대로 배열된다.
본 발명에 따르면 진공증착법을 적용하여 유전체와 전극의 두께를 현저하게 감소시킬 수 있으며, 제한된 공간내에서 전극의 겹침면적을 최대화할 수 있어 초고용량의 캐패시터를 제공할 수 있다.
트랜치 구조, 증착, 식각, 캐패시터, 수직전극-
公开(公告)号：KR1020080071701A
公开(公告)日：2008-08-05
申请号：KR1020070009913
申请日：2007-01-31
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: A multilayer chip capacitor is provided to stabilize a power circuit of an MPU(Micro-Processor Unit) package by increasing the number of decoupling capacitors connected in parallel in a predetermined mounting area of the package and reducing total inductance. A multilayer chip capacitor(100) includes a main body(121), at least three pairs of first and second outer electrodes(131-138), and a plurality of first and second inner electrodes. The main body is formed in a rectangular parallelepiped shape by stacking a plurality of dielectric layers. The first and second outer electrodes are alternately arranged on two longer side faces opposite to the main body, have different polarity, and face each other. The first and second inner electrodes are alternately arranged in the main body, are divided by the dielectric layers and are connected to the first and second outer electrodes through a lead respectively.
Abstract translation: 提供了一种多层片状电容器，用于通过增加在封装的预定安装区域中并联连接的去耦电容器的数量来稳定MPU（微处理器单元）封装的电源电路，并降低总电感。 多层片状电容器（100）包括主体（121），至少三对第一和第二外部电极（131-138）以及多个第一和第二内部电极。 主体通过堆叠多个电介质层而形成为长方体形状。 第一外电极和第二外电极交替地布置在与主体相对的两个较长侧面上，具有不同的极性，并且彼此面对。 第一和第二内部电极交替地布置在主体中，被电介质层分开，并且分别通过引线连接到第一和第二外部电极。
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公开(公告)号：KR100835051B1
公开(公告)日：2008-06-03
申请号：KR1020060004592
申请日：2006-01-16
Applicant: 삼성전기주식회사
Abstract: 저ESL을 구현할 수 있는 적층형 커패시터가 제공된다.
본 발명의 커패시터는,
유전체를 사이에 두고 제1내부전극과 제2내부전극이 교대로 적층되고, 측면에는 상하 방향으로 홈이 형성되는 커패시터 본체,
상기 커패시터 본체의 홈에 형성되는 외부전극으로 구성되고,
상기 제1내부전극과 제2내부전극의 측변에는 상기 홈의 외부전극과 접촉하는 접촉부를 구비하고, 제1내부전극의 접촉부와 제2내부전극의 접촉부는 인접하여 교대로 배치되는 것을 포함하여 이루어진다.
적층형 커패시터, ESL, 홈, 배선기판-
公开(公告)号：KR100809239B1
公开(公告)日：2008-03-07
申请号：KR1020060137587
申请日：2006-12-29
Applicant: 삼성전기주식회사
CPC classification number: H01G4/232 , H01G4/005 , H01G4/30 , H03H2001/0014
Abstract: A multilayer capacitor array is provided to suppress cross talk by controlling width and length of negative and positive inner electrodes even in case of alignment of the inner electrodes and to facilitate layout arrangement of a wiring path of a circuit board for mounting the capacitor array. A multilayer capacitor array includes a capacitor main body(61), first and second polarity inner electrodes(65a-68a), and first and second polarity outer electrodes(65-68). The capacitor main body is formed by stacking a plurality of dielectric layers and has first and second sides to face each other. The first and second polarity inner electrodes are arranged between the dielectric layers in the capacitor main body to face each other and are composed of a single electrode plate having a lead respectively. The first and second polarity outer electrodes are formed on the first and second sides respectively and connected to the corresponding polarity inner electrodes through the lead. The capacitor array has a plurality of multilayer capacitor elements formed inside a multilayer structure.
Abstract translation: 提供了一种层叠电容器阵列，即使在内电极对准的情况下也通过控制负极和正内电极的宽度和长度来抑制串扰，并且便于用于安装电容器阵列的电路板的布线路径的布局布置。 多层电容器阵列包括电容器主体（61），第一和第二极性内部电极（65a-68a）以及第一和第二极性外部电极（65-68）。 电容器主体通过堆叠多个电介质层而形成，并且具有第一和第二侧面对面。 第一和第二极性内部电极被布置在电容器主体中的电介质层之间彼此面对，并且分别由具有引线的单个电极板构成。 第一和第二极性外部电极分别形成在第一和第二侧上，并通过引线连接到相应的极性内部电极。 电容器阵列具有形成在多层结构内的多个多层电容器元件。
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