公开(公告)号：KR1020140057993A

公开(公告)日：2014-05-14

申请号：KR1020120124424

申请日：2012-11-05

Applicant: 삼성전자주식회사

Inventor： 장재준

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/02233 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681

Abstract: Provided are semiconductor device and a method of manufacturing same. The semiconductor device includes a semiconductor substrate; a first well of a first conductive type placed in the semiconductor substrate; a drift region of a second conductive type placed in the semiconductor substrate, and having first and second drift doping regions, wherein the first and second drift doping regions overlap the first well; and a body region of the first conductive type placed in the first well and making contact with the first drift doping region. The first and second drift doping regions include first and second conductive dopants. An average concentration of the first conductive dopant in the first drift doping region is less than that of the first conductive dopant in the second drift doping region.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括半导体衬底; 放置在半导体衬底中的第一导电类型的第一阱; 位于所述半导体衬底中的具有第一和第二漂移掺杂区的第二导电类型的漂移区，其中所述第一和第二漂移掺杂区与所述第一阱重叠; 以及放置在第一阱中并与第一漂移掺杂区接触的第一导电类型的体区。 第一和第二漂移掺杂区域包括第一和第二导电掺杂剂。 第一漂移掺杂区域中的第一导电掺杂剂的平均浓度小于第二漂移掺杂区域中的第一导电掺杂剂的平均浓度。

公开(公告)号：KR1020130142789A

公开(公告)日：2013-12-30

申请号：KR1020120066315

申请日：2012-06-20

Applicant: 삼성전자주식회사

Inventor： 장재준 ,  김민환 ,  장동은 ,  장훈

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66681

Abstract: The present invention provides a semiconductor device having a power MOS transistor capable of minimizing the calorific value and improving the reliability. The semiconductor device having a power MOS transistor according to the present invention comprises a semiconductor substrate in which an impurity region having a first conductivity is formed; a drift region which is formed in the impurity region and has the first conductivity; a body region which is formed in the impurity region to be adjacent to the drift region and has a second conductivity different from the first conductivity; a drain extension insulating film which is formed on the drift region; a gate insulating film and a gate electrode which are sequentially laminated on the semiconductor substrate to straddle a part of the body region and a part of the drift region; a drain extension electrode which is formed on the drain extension insulating film; a drain region which is adjacent to one side opposite to the body region in the drift region and has the first conductivity; and a second source which is formed in the body region and has the second conductivity.

Abstract translation: 本发明提供一种具有功率MOS晶体管的半导体器件，其能够使发热量最小化并提高可靠性。 具有根据本发明的功率MOS晶体管的半导体器件包括其中形成具有第一导电性的杂质区的半导体衬底; 漂移区，形成在杂质区并具有第一导电性; 形成在与所述漂移区相邻的所述杂质区中并具有与所述第一导电性不同的第二导电性的体区; 漏极延伸绝缘膜，形成在漂移区上; 栅绝缘膜和栅电极，其依次层叠在半导体基板上，跨越体区的一部分和漂移区的一部分; 漏极延伸电极，形成在漏极延伸绝缘膜上; 漏极区域，其与所述漂移区域中的所述体区域相对的一侧相邻并且具有所述第一导电性; 以及形成在体区中并具有第二导电性的第二源。

公开(公告)号：KR1020130123153A

公开(公告)日：2013-11-12

申请号：KR1020120046349

申请日：2012-05-02

Applicant: 삼성전자주식회사

Inventor： 장훈 ,  장재준

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

Abstract: The present invention relates to a semiconductor device comprising a first conductive substrate; a drain region and a source region separately formed on the substrate; a first conductive body region formed at the substrate to surround the side and the lower surface of the source region; a second conductive drift region formed at the substrate to surround the side and the lower surface of the drain region; a first gate formed on the body region; and a second gate formed on the drift region while being separated from the first gate and electrically floated.

Abstract translation: 本发明涉及一种包括第一导电衬底的半导体器件; 分别形成在所述基板上的漏极区域和源极区域; 形成在所述基板上以围绕所述源极区域的所述侧面和所述下表面的第一导电体区域; 形成在所述基板上以围绕所述漏极区域的所述侧面和所述下表面的第二导电漂移区; 形成在身体区域上的第一门; 以及形成在所述漂移区上同时与所述第一栅极分离并电浮动的第二栅极。