公开(公告)号：KR1020090018252A

公开(公告)日：2009-02-20

申请号：KR1020070082549

申请日：2007-08-17

Applicant: 삼성전자주식회사

Inventor： 조남필 ,  공준진 ,  윤찬호 ,  채동혁 ,  조경래

IPC: H03M13/00 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

Abstract: A decoder and a decoding method are provided to raise throughput by using a double buffering structure and a pipelining technique. While a first code word is transmitted to the first memory, first syndrome values are calculated from the first code word(S1). While an error locator polynomial is calculated from the first syndrome values, a second coding word is transmitted to a second memory and second syndrome values are calculated from the second code word(S3).

Abstract translation: 提供解码器和解码方法，以通过使用双缓冲结构和流水线技术来提高吞吐量。 当第一码字被发送到第一存储器时，从第一码字（S1）计算第一校正子值。 虽然从第一个校正子值计算了错误定位多项式，但是第二编码字被发送到第二存储器，并且从第二代码字（S3）计算出第二校正子值。

公开(公告)号：KR1020080053787A

公开(公告)日：2008-06-16

申请号：KR1020060125739

申请日：2006-12-11

Applicant: 삼성전자주식회사

Inventor： 조남필

IPC: G06F11/10 ,  G06F11/08 ,  G06F12/00 ,  G06F11/36

CPC classification number: G06F11/10

Abstract: A firmware download scheme capable of correcting error is provided to correct the error of firmware downloaded from a host to an electronic device based on an ECC(Error Checking and Correction) and CRC(Cyclic Redundancy Check) bits included in a firmware data signal packet received from the host, thereby increasing integrity of the firmware. An interface(210) receives a firmware data signal including an ECC(Error Correction Code) from the outside. An ECC unit(250) corrects error included in the firmware data signal and stores the corrected data signal to a non-volatile memory(260) such as a flash memory. A buffer(220) temporarily stores the firmware data signal received through the interface. The error correction circuit corrects the error included in the firmware data signal stored in the buffer by control of a CPU(240). A firmware data signal packet received from the outside includes data, and ECC and CRC(Cyclic Redundancy Check) bits.

Abstract translation: 提供能够纠正错误的固件下载方案，用于根据收到的固件数据信号包中包含的ECC（错误检查和校正）和CRC（循环冗余校验）比特来校正从主机下载到电子设备的固件的错误 从主机，从而增加固件的完整性。 接口（210）从外部接收包括ECC（纠错码）的固件数据信号。 ECC单元（250）校正固件数据信号中包括的错误，并将校正的数据信号存储到诸如闪存的非易失性存储器（260）。 缓冲器（220）临时存储通过接口接收的固件数据信号。 错误校正电路通过CPU（240）的控制来校正存储在缓冲器中的固件数据信号中包括的错误。 从外部接收的固件数据信号包包括数据，ECC和CRC（循环冗余校验）位。

公开(公告)号：KR1020080013156A

公开(公告)日：2008-02-13

申请号：KR1020060074291

申请日：2006-08-07

Applicant: 삼성전자주식회사

Inventor： 조남필 ,  심규현 ,  양신호 ,  손창일

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F1/00

CPC classification number: G06F12/0246 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/385 ,  G06F13/423 ,  G06F2003/0697

Abstract: A memory card system, a data transmitting method of the memory card system, and a semiconductor memory device are provided to transmit data to a host in synchronization with a read clock signal generated by an internal clock generator of a memory card to maintain a set-up time margin sufficient for a read operation. A memory card system(200) includes a host(210) and a memory card(220). The host generates a read command. The memory card generates an internal read clock signal in response to the read command and transmits data to the host in synchronization with the read clock signal. The memory card includes a read clock generator(224) for generating the read clock signal. The host includes a write clock generator. When the host stores data in the memory card, the memory card stores the data in synchronization with the write clock signal generated by the write clock generator.

Abstract translation: 提供存储卡系统，存储卡系统的数据发送方法和半导体存储器件，以与由存储卡的内部时钟发生器产生的读取时钟信号同步地向主机发送数据， 上升时间裕度足以用于读取操作。 存储卡系统（200）包括主机（210）和存储卡（220）。 主机生成读命令。 存储卡响应于读取命令产生内部读取时钟信号，并与读取的时钟信号同步地向主机发送数据。 存储卡包括用于产生读时钟信号的读时钟发生器（224）。 主机包括写时钟发生器。 当主机将数据存储在存储卡中时，存储卡将数据与由写入时钟发生器产生的写时钟信号同步存储。

公开(公告)号：KR100791839B1

公开(公告)日：2008-01-07

申请号：KR1020060106184

申请日：2006-10-31

Applicant: 삼성전자주식회사

Inventor： 조남필

IPC: G11C16/10

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C16/26

Abstract: A non-volatile memory device for generating a data strobe signal during data read operation and a method thereof are provided to assure proper data set-up time margin and data hold time margin even though read cycle time decreases. A non-volatile memory device comprises a latch unit(220), a non-volatile memory cell array(310) for storing data and a control unit. The control unit receives a read command and a read address outputted from a memory controller(200), and generates a data strobe signal on the basis of the received read command, and reads data corresponding to the received read address from the non-volatile memory cell array, and outputs the read-out data to the latch unit. The latch unit outputs data outputted from the control unit to the memory controller in response to the data strobe signal.

Abstract translation: 提供用于在数据读取操作期间产生数据选通信号的非易失性存储器件及其方法，以确保即使读取周期时间减少，适当的数据建立时间裕度和数据保持时间裕度。 非易失性存储器件包括锁存单元（220），用于存储数据的非易失性存储单元阵列（310）和控制单元。 控制单元接收从存储器控制器（200）输出的读取命令和读取地址，并且基于接收到的读取命令生成数据选通信号，并且从非易失性存储器读取与所接收的读取地址相对应的数据 单元阵列，并将读出的数据输出到锁存单元。 锁存单元响应于数据选通信号将从控制单元输出的数据输出到存储器控制器。