公开(公告)号：KR1020080056883A

公开(公告)日：2008-06-24

申请号：KR1020060130010

申请日：2006-12-19

Applicant: 전북대학교산학협력단

Inventor： 김형석 ,  손홍락

IPC: H03M13/41

CPC classification number: H03M13/6597 ,  H03M13/41 ,  H03M13/42 ,  H03M13/6502 ,  H04L1/0053

Abstract: A high performance Viterbi decoder structure with a 2-dimensional analog signal processing cell array and a multiplexer and a method thereof are provided to perform high speed decoding by executing hardware decoding using electrical signals. A high performance Viterbi decoder structure includes a 2-dimensional analog signal processing cell array, capacitors(150), and a multiplexer(250). The 2-dimensional analog signal processing cell array includes a mashed analog electronic circuit based on analog signal processing cells(110). The capacitors are implemented as much as the number of stages of the analog signal processing cells so as to store input signals. The multiplexer connects the capacitors to the 2-dimensional analog signal processing cell array based on an input sequence of information stored in the capacitors.

Abstract translation: 提供具有2维模拟信号处理单元阵列的高性能维特比解码器结构以及多路复用器及其方法，以通过使用电信号执行硬件解码来执行高速解码。 高性能维特比解码器结构包括二维模拟信号处理单元阵列，电容器（150）和多路复用器（250）。 二维模拟信号处理单元阵列包括基于模拟信号处理单元（110）的捣碎模拟电子电路。 电容器的实现与模拟信号处理单元的级数一样多，以便存储输入信号。 多路复用器基于存储在电容器中的信息的输入序列将电容器连接到二维模拟信号处理单元阵列。