Abstract:
PURPOSE: A near field communication processing system improving the compatibility of communication environment for processing the multi biosignal is provided to secure health condition in desired time by supplying various bio signals in real time and analyzing it. CONSTITUTION: In a near field communication processing system improving the compatibility of communication environment for processing the multi bio signal, a receiving unit receives body information data. A data frame confirmation unit decides the conversion of the data frame form. A library DB stores the form information of data frame. The converting unit changes a standard form after analyzing a search result. A data classification unit(210) classifies the body information from body information data. A storage unit(220) stores the body information. A data analysis unit(230) analyzes the saved body information. A controller transmits the analyzed result to an output station(40).
Abstract:
PURPOSE: A backlight control device and a backlight controlling method are provided to improve image quality and reduce power consumption by controlling the brightness of a backlight using brightness information between divided sections of the backlight. CONSTITUTION: An image signal processor(110) produces the maximum section brightness control value from an image signal. A control signal generator(120) corrects the produced section brightness value and produces a backlight control value. An image signal controller(130) controls the image signal.
Abstract:
본 발명은 표시 장치 및 방법에 관한 것으로서, 구체적으로는 소비 전력 절감을 위한 백라이트 로컬 디밍 제어시 영상의 화질 열화 현상을 보상할 수 있도록 한 표시 장치 및 방법에 관한 것이다. 이와 같은 본 발명은, 입력 영상신호를 분석하여 분할된 표시 영역의 블록별 밝기 정보를 추출하는 영상 분석부; 상기 밝기 정보를 통해 상기 표시 영역의 블록에 대응하는 백라이트 블록별 백라이트 제어값을 연산하는 블록 제어값 연산부; 및 인접 블록의 밝기 정도를 고려한 상기 각 백라이트 블록의 밝기에 따라 소정 비율로 밝기 정도를 낮추는 스케일링 수행여부를 결정하여 백라이트 보상 제어값을 출력하는 블록 제어값 보상부를 포함하는 표시 장치 및 그를 이용한 표시방법을 제공한다. 백라이트, 백라이트 블록, 디밍 제어, 블록킹 현상, 밝기
Abstract:
A device for controlling the brightness of a backlight of an image displaying device is provided to decrease the operation quantity when controlling the brightness of the backlight according to the brightness of video data is reduced and to reduce the backlight turnaround time. A full search step decides the brightness control value and selects the standard block as the M x N corresponded to the backlight about the input image frame whole(S111). A partial search step determines the brightness control value after the full search step about the inputted video frame before the input of the video frame against the anchor block and peripheral block of the inputted video frame and presently selects again the standard block(S113). A brightness regulating step controls the brightness of the backlight by the adjustment value determined on the partial search step and full search step(S130).
Abstract:
An IDFT(Interconnect Delay Fault Test) controller and an IDFT device using the same are provided to simultaneously test a delay fault of several interconnect lines using different system clocks or core clocks, through one test cycle correspondingly to each system clock or core clock even if plural system clocks or core clocks exist. IDFT controllers(140,240) generate a control signal for testing an interconnect delay fault between BSCs(Boundary Scan Cells) by using IEEE(Institute of Electrical and Electronics Engineers) 1491.1 standard. The IDFT controller receives a data register shift signal(ShiftDR), a data register update signal(UpdateDR), and a data register clock signal(ClockDR) of IEEE 1491.1 standard and generates an update signal(UpDR) and a capture signal(CapDR) on the basis of a system clock(SysCLK) to perform updating and capturing within one system clock range in the BSC.
Abstract translation:提供IDFT(互连延迟故障测试)控制器和使用该IDFT的IDFT设备,以通过与每个系统时钟或核心时钟对应的一个测试周期来同时测试使用不同系统时钟或核心时钟的多条互连线路的延迟故障,即使 存在多个系统时钟或核心时钟。 IDFT控制器(140,240)通过使用IEEE(Institute of Electrical and Electronics Engineers)1491.1标准生成用于测试BSC(边界扫描单元)之间的互连延迟故障的控制信号。 IDFT控制器接收数据寄存器移位信号(ShiftDR),数据寄存器更新信号(UpdateDR)和IEEE 1491.1标准的数据寄存器时钟信号(ClockDR),并产生更新信号(UpDR)和捕获信号(CapDR) 基于在BSC中的一个系统时钟范围内执行更新和捕获的系统时钟(SysCLK)。
Abstract:
PURPOSE: A high-speed 8bit/10bit encoder/decoder for increasing a data processing speed by applying a two-stage logic synthesis method to a logic gate structure is provided to perform rapidly and stably a processing operation by minimizing processing steps. CONSTITUTION: A 5bit/6bit encoding function block is used for calculating output data of 6 bits having same number of 0 and 1 by using input data of 5 bits. A 3bit/4bit encoding function block is used for calculating output data of 4 bits having same number of 0 and 1 by using input data of 3 bits. A disparity calculation block is used for generating and outputting a disparity(160) in response to an output and a clock of a 8bit/10bit encoding function block.