公开(公告)号：KR100417136B1

公开(公告)日：2004-02-05

申请号：KR1020010019861

申请日：2001-04-13

Applicant: 한국전자통신연구원

Inventor： 김원종 ,  장준영 ,  이광엽 ,  배영환 ,  정교일

IPC: G06F7/00

Abstract: PURPOSE: A device and a method for multiplying the finite fields on a polynomial basis are provided to offer a small volume circuit by using a digit serial mode in the finite fields multiplication of high degree polynomial and to realize the fast multiplication by using a fast clock generator deferent from the system clock. CONSTITUTION: The first storing tool stores a multiplier, a multiplicand and a product as the operation result by dividing into a digit unit. The second storing tool(15) assists the operation by storing a middle value necessary for a process carrying out the operation in the first storing tool and stores the final result. An address generating tool(16) generates an address of the second storing tool for writing or reading the value necessary for the first storing tool from the second storing tool. A clock generating tool(17) provides the fast clock operated by being separated from the system clock to the first storing tool.

Abstract translation: 目的：提供一种在多项式基础上乘以有限域的设备和方法，通过在高阶多项式的有限域乘法中使用数字串行模式提供小体积电路，并通过使用快速时钟实现快速乘法 发生器不同于系统时钟。 组成：第一个存储工具将乘数，被乘数和乘积存储为一个数字单位作为运算结果。 第二存储工具（15）通过在第一存储工具中存储执行操作的处理所需的中间值来辅助操作并存储最终结果。 地址生成工具（16）生成用于从第二存储工具写入或读取第一存储工具所需的值的第二存储工具的地址。 时钟生成工具（17）将通过从系统时钟分离而操作的快速时钟提供给第一存储工具。

公开(公告)号：KR1020030062070A

公开(公告)日：2003-07-23

申请号：KR1020020002491

申请日：2002-01-16

Applicant: 한국전자통신연구원

Inventor： 김승철 ,  김원종 ,  조한진

IPC: G11C16/06

Abstract: PURPOSE: A flash memory access control device and a method for the same are provided to supply the write-pulse type without incorporating an inner display function or a control circuit thereinto. CONSTITUTION: A flash memory access control device(110) includes a control signal generation block(101), a limited state control block(102) and a reset delay block(103). In the flash memory access control device(110), the limit state control block(102) outputs the signal corresponding to the operational mode by comparing with the current state and determining the following state to be changed after analyzing the contents of the command transmitted from the address and the data. The control signal generation block(101) outputs the control signal so as to operate the flash memory as the corresponding mode in response to the signal outputted from the limited state control block(102). And, the reset delay block(103) cancels the reset state of the flash memory in response to the reset cancellation signal inputted from the active unit and outputs the reset cancellation signal delayed by a predetermined time to the limited state control block(102) and the control signal generation block(101), respectively.

Abstract translation: 目的：提供一种闪存存取存取控制装置及其方法，以便在不附加内部显示功能或控制电路的情况下提供写脉冲型。 构成：闪速存储器访问控制装置（110）包括控制信号生成块（101），有限状态控制块（102）和复位延迟块（103）。 在闪速存储器访问控制装置（110）中，极限状态控制块（102）通过与当前状态进行比较来输出与操作模式相对应的信号，并且在分析从 地址和数据。 控制信号产生块（101）响应于从限制状态控制块（102）输出的信号，输出控制信号，以便操作闪速存储器作为相应的模式。 并且，复位延迟块（103）响应于从有源单元输入的复位消除信号而取消闪速存储器的复位状态，并将延迟了预定时间的复位消除信号输出到限制状态控制块（102），并且 控制信号生成块（101）。