Abstract:
The present invention relates to a distortion correcting device. The present invention relates to technology capable of constantly maintaining linearization performance regardless of a set value of a target gain with regard to a power amplifier by extracting a specific curve of the power amplifier after a single tone signal is inserted into a protection band of an OFDM symbol. The distortion correcting device according to the present invention includes an OFDM modulation unit and an RF transmitting unit.
Abstract:
이동 멀티홉 릴레이를 이용한 상향 액세스 링크 전력 제어 방법 및 그 시스템이 개시된다. 기지국이 상향 액세스 링크의 전력 제어 주체를 자신으로 결정한 경우, 멀티홉 릴레이로부터 보고받는 채널품질특성정보를 기초로 액세스 링크의 전력 제어를 위한 메시지를 생성하여 단말로 전송하고, 기지국이 상향 액세스 링크의 전력 제어 주체를 멀티홉 릴레이로 결정한 경우, 멀티홉 릴레이가 채널품질특성정보를 기초로 액세스 링크의 전력 제어를 위한 메시지를 생성하여 단말로 전송함으로써, 상향 액세스 링크의 전력 제어를 고속으로 할 수 있다. 이동 멀티홉 릴레이, 상향 액세스 링크, 채널품질
Abstract:
PURPOSE: A digital predistortion compensating apparatus for preventing divergence of an output of an amplifier and a method using the same are provided to secure the linearity of the amplifier by preventing diverging the output of the amplifier. CONSTITUTION: A digital predistortion compensating apparatus(10) includes a digital predistortion filter, a power amplifier(40), and a filter coefficient control unit. The digital predistortion filter receives a predistortion coefficient and predistorts an input signal. The power amplifier amplifies an output of a predistorter. The filter coefficient control unit receives a coupled signal among the input signal and the output of the power amplifier, performs a previously stored algorithm, calculates a filter coefficient and provides the filter coefficient to the digital predistortion filter. [Reference numerals] (10) DPD compensator; (100) DPP filter; (220) DPD algorithm execution unit; (240) Filter coefficient providing unit; (30) RF up converter; (40) Power amplifier; (50) RF down converter
Abstract:
PURPOSE: A digital pre-distortion(DPD) amplifying device in a multiple antenna system is provided to prevent the increase of system sizes and costs by sharing a DPD feedback path and a DPD algorithm processing part. CONSTITUTION: Correcting parts(411 to 414) pre-distort input signals to be output and output the pre-distorted signals through antennas(441 to 444). Power amplifiers(431 to 434) are in connection with the correcting parts and amplify and output the pre-distorted signals. A distorted information extractor(450) extracts distorted information from feedback signals from the power amplifiers and from the input signals and output the distorted information to the correcting parts.
Abstract:
PURPOSE: An apparatus for reducing envelope distortion in a power amplifier is provided to eliminate a discontinuous properties from an envelope signal by applying a predistorter to an ET(Envelope Tracking) power amplifier. CONSTITUTION: A power amplifier comprises a power amplifier amplifying an input signal to be wirelessly transmitted through an antenna, a bias changing device changing a voltage of a bias signal according to a size of the input signal, and a DPD(Digital Pre-Distorter) performing predistortion. An envelop generation device comprises a signal size generation unit(710) and a correction unit(720). The signal size generation unit generates a size of a pre-distorted input signal. The signal size generation unit generates a pre-distorted envelope signal. The correction unit revises the generated envelope signal.
Abstract:
PURPOSE: A PAPR(Peak to Average Power Ratio) reduction apparatus and orthogonal frequency division multiplexing system for the same are provided to reduce the PAPR phenomenon of a signal that is modulated in two or more modulation methods. CONSTITUTION: A clipping level determining unit(620) determines a clipping level for PAPR reduction based on complex modulation method information and average voltage of a modulated signal. A clipping unit(600) clips the signal which is complexly modulated to the determined clipping level. The clipping level determining unit receives the average voltage from a modulating unit. The clipping unit performs nonlinear clipping by using a log function.
Abstract:
PURPOSE: A pre-distortion device of a power amplifier and a method thereof are provided to fix a bias voltage of a power amplifier while a complex correction coefficient is updated, thereby distortion of a signal outputted from the power amplifier. CONSTITUTION: A pre-distortion unit(210) calculates the size of an input signal. The pre-distortion unit generates a pre-distortion signal of the input signal by outputting a complex correction coefficient corresponding to the size of the input signal. The pre-distortion unit provides the generated pre-distortion signal as input of the power amplifier. A complex correction coefficient updating unit(240) generates an error signal by comparing an output signal with the input signal of the power amplifier. The complex correction coefficient updating unit updates the complex correction coefficient to minimize the size of the generated error signal. The pre-distortion unit provides a fixed bias voltage value to the power amplifier while the complex correction coefficient is updated.
Abstract:
본 발명은 유한체 내에서 역원 계산 장치 및 방법에 관한 것이다. 외부로부터 입력되는 원시 원소에 대하여 유한체 지수승 블록 및 곱셈 블록으로 구성된 지수승 연산부를 이용하여 임의의 원소에 대한 역원을 계산함으로써, 하드웨어의 자원을 절약할 수 있을 뿐만 아니라, 역원을 구하는 연산 속도도 증가시킬 수 있다. 유한체, 곱셈, 역원, 표준기저
Abstract:
본 발명은 역믹스컬럼블록 장치 및 이를 이용한 곱셈연산방법에 관한 것이다. 본 발명에 따르면, 역믹스컬럼블록 장치는 비트 단위의 입력 데이터를 바이트 단위로 저장하여 출력하는 저장부, 저장부로부터 입력받은 입력 바이트에 대한 16진수 값인 {01}, {02}, {04} 및 {08} 곱셈연산을 수행하여 출력하는 제1 곱셈연산 블록부, 제1 곱셈연산 블록부로부터 입력받은 {01}, {02}, {04} 및 {08} 곱셈연산 결과를 이용하여 {09}, {0b}, {0d} 및 {0e} 곱셈연산을 수행하여 출력하는 제2 곱셈연산 블록부 및 제2 곱셈연산 블록부로부터 입력받은 {09}, {0b}, {0d} 및 {0e} 곱셈연산 결과에 대한 배타적 논리합 연산을 수행하여 출력 바이트를 출력하는 배타적 논리합 연산부를 포함한다. 이와 같이, 곱셈기로 구성된 역믹스컬럼블록 장치를 간단한 하드웨어로 구현함으로써 암호화 성능을 향상시켜, 소형, 저전력 휴대기기에 쉽게 적용할 수 있다. AES, 복호화, 역믹스컬럼블록,