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公开(公告)号：AU5954494A
公开(公告)日：1994-08-15
申请号：AU5954494
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： BRUNT ROGER VAN , OPRESCU FLORIN
IPC: G06F13/378 , G06F13/40 , H03K19/0175 , H03M5/16 , H03M5/18 , H04L25/02 , H04L25/49
Abstract: The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus across the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a height transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving an input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.
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公开(公告)号：CA2415289A1
公开(公告)日：1994-07-21
申请号：CA2415289
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , VAN BRUNT ROGER
Abstract: The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has as a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus across the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a high transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving as input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.
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公开(公告)号：CA2503597C
公开(公告)日：2010-06-29
申请号：CA2503597
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F13/36 , G06F15/16 , G06F13/00 , G06F13/14 , G06F13/362 , G06F13/40 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64 , H04L29/12
Abstract: A node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an a priori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.
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公开(公告)号：CA2408252C
公开(公告)日：2005-07-26
申请号：CA2408252
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F13/368 , G06F13/00 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent-child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
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公开(公告)号：DE69432587T2
公开(公告)日：2004-03-25
申请号：DE69432587
申请日：1994-01-12
Applicant: APPLE COMPUTER
Inventor： VAN BRUNT ROGER , OPRESCU FLORIN
Abstract: The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as desired, to generate additional clock signals delayed by 5- or 10-nanosecond intervals.
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Patent Agency Ranking
公开(公告)号：HK1037035A1
公开(公告)日：2002-01-25
申请号：HK01107369
申请日：2001-10-22
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F20060101 , G06F13/00 , G06F13/368 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgement priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always asserts its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initilialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
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公开(公告)号：DE69428885D1
公开(公告)日：2001-12-06
申请号：DE69428885
申请日：1994-01-12
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , VAN BRUNT W
Abstract: A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus configuration for arbitration like a single bus. Following arbitration, the interconnected nodes provide a second configuration for high speed unidirectional data transfer without the bandwidth limitations of a single bus. Each node includes an arbiter, a data bus, a plurality of ports, a first multiplexer to select either the arbiter or the data bus, and a second multiplexer to select either the arbiter or the data bus. The data bus includes a transmit bus and a receive bus that are coupled with a repeater circuit that can resynchronize the data. During arbitration, the multiplexers select the arbiter to provide the function of a single bus for all the nodes. During data transfer, the multiplexers are configured for transmission of data. Furthermore, a node can function as a repeater and resynchronizer even if it is not connected to a local host or if the local host is turned off or otherwise nonoperational.
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公开(公告)号：AU6446594A
公开(公告)日：1994-10-11
申请号：AU6446594
申请日：1994-03-11
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , BRUNT ROGER VAN
Abstract: In a computer bus arrangement in which a plurality of nodes are interconnected by communication links, control signals are exchanged between the nodes concerning the transmission rate of a data message to be transmitted and the reception rate capability of the nodes. The data message is passed to those nodes which have a reception rate capability which matches or exceeds the transmission rate associated with the message. The other nodes receive a mock data message at a rate within their capability. In order to aid in synchronization within the bus arrangement, the duration of the mock data message is the same as the data message received by the other nodes, even though they are transmitted at different rates.
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39.发明专利
公开(公告)号：AU6405894A
公开(公告)日：1994-10-11
申请号：AU6405894
申请日：1994-03-11
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , BRUNT ROGER VAN
Abstract: The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfer of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. The ternary receiver comprises two binary receivers for detecting resultant current amplitudes created on the bus during simultaneous driving of control signals by the nodes during the control transfer phases and logic means for combining the resultant current amplitudes on the bus with the signal states driven by the local transceiver to output reconstructed control signals representing the control signals driven on the bus by the corresponding transceiver. Furthermore, both transceivers further include a preemptive signaling receiver for the detection of preemptive control messages which act to terminate the data transfer phases upon receipt of the message so that higher priority control transfers may take place.
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40.发明专利
公开(公告)号：CA2158155A1
公开(公告)日：1994-09-29
申请号：CA2158155
申请日：1994-03-11
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , VAN BRUNT ROGER
Abstract: The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfert of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. The ternary receiver comprises two binary receivers for detecting resultant current amplitudes created on the bus during simultaneous driving of control signals by the nodes during the control transfer phases and logic means for combining the resultant current amplitudes on the bus with the signal states driven by the local transceiver to output reconstructed control signals representing the control signals driven on the bus by the corresponding transceiver. Furthermore, both transceivers further include a preemptive signaling receiver for the detection of preemptive control messages which act to terminate the data transfer phases upon receipt of the message so that higher priority control transfers may take place.
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