公开(公告)号：JP2006229992A

公开(公告)日：2006-08-31

申请号：JP2006051934

申请日：2006-02-28

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  H04L12/28 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64

CPC classification number: H04L12/40078 ,  G06F13/36 ,  G06F13/37 ,  G06F15/17343 ,  H04L12/40084 ,  H04L45/48

Abstract: PROBLEM TO BE SOLVED: To establish communication between respective nodes in the system where an arbitrary assembly of nodes on a system bus is resolved into an acyclic directed graph. SOLUTION: A configuration bus access arbitration scheme, a priority bus access arbitration scheme, a token passing bus arbitration scheme and a preemptive bus initialization mechanism, etc. are implemented. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：建立系统中各个节点之间的通信，其中系统总线上的节点的任意组合被分解成非循环有向图。 解决方案：实现配置总线访问仲裁方案，优先总线访问仲裁方案，令牌传递总线仲裁方案和抢占总线初始化机制等。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006238452A

公开(公告)日：2006-09-07

申请号：JP2006051942

申请日：2006-02-28

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  H04L12/44 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04L12/64

CPC classification number: H04L12/40078 ,  G06F13/36 ,  G06F13/37 ,  G06F15/17343 ,  H04L12/40084 ,  H04L45/48

Abstract: PROBLEM TO BE SOLVED: To provide a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph and communication between the nodes is established. SOLUTION: The constituent bus access arbitration scheme, the preferential bus access arbitration scheme, the token passing bus arbitration scheme, and the preemptive bus initialization mechanism or the like are implemented. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种系统，其中系统总线上的节点的任意组合已被解析成非循环有向图，并且建立节点之间的通信。 解决方案：实现了组成总线访问仲裁方案，优先总线访问仲裁方案，令牌通过总线仲裁方案和抢占式总线初始化机制等。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005168062A

公开(公告)日：2005-06-23

申请号：JP2005045358

申请日：2005-02-22

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN ,  VAN BRUNT ROGER

IPC: G06F3/00 ,  H04L5/14 ,  H04L12/40 ,  H04L25/03 ,  H04L25/38

CPC classification number: H04L5/1423 ,  H04L12/4135

Abstract: PROBLEM TO BE SOLVED: To provide a bus transceiver, in which a high speed binary transfer mode for half-duplex binary transfer of data signals is combined with a ternary control transfer mode, having a full-duplex dominant logic transmission scheme for full-duplex transfer of control signals. SOLUTION: This transceiver for communications via a transmission channel has a receiver connected to the transmitting channel, and the receiver receives data, according to a binary signal status driven on the transmitting channel from the transmitting channel in the first mode, and receives data, according to a ternary signal status driven on the transmitting channel from the transmission channel in the second mode. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种总线收发器，其中用于数据信号的半双工二进制传输的高速二进制传输模式与三进制控制传输模式组合，具有全双工主导逻辑传输方案，用于 全双工传输控制信号。 解决方案：用于经由传输信道进行通信的收发机具有连接到发射信道的接收机，并且接收机根据在第一模式下从发射信道在发射信道上驱动的二进制信号状态接收数据，并且接收 数据，根据在第二模式中从传输信道在发送信道上驱动的三进制信号状态。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004030648A

公开(公告)日：2004-01-29

申请号：JP2003158059

申请日：2003-06-03

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64

CPC classification number: H04L12/40078 ,  G06F13/36 ,  G06F13/37 ,  G06F15/17343 ,  H04L12/40084 ,  H04L45/48

Abstract: PROBLEM TO BE SOLVED: To establish communication between nodes in a system in which an optional assembly of nodes along a system bus is changed to a non-cyclic directed graph.
SOLUTION: A structure bus access arbitration system, a priority bus access arbitration system, a token passing bus arbitration system and a pre-emptive bus initialization setting mechanism, etc. are executed.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004362620A

公开(公告)日：2004-12-24

申请号：JP2004277631

申请日：2004-09-24

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN ,  TEENER MICHAEL D

IPC: G06F1/26 ,  G06F1/32 ,  G06F3/00

CPC classification number: G06F1/3203 ,  G06F1/325

Abstract: PROBLEM TO BE SOLVED: To provide power management ability to a device interconnection bus with which a plurality of devices are connected. SOLUTION: This power management system tracks the total power drawn from a bus by the bus and a device connected to the bus itself and the maximum power usable from the bus based on individual operational status of each device. Whether or not there is sufficient excess power for additionally operating the device is determined from the information. Efficient use of limited power is provided so that many devices are operated while maintaining draw of the total power within an allowable range. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004326756A

公开(公告)日：2004-11-18

申请号：JP2004112136

申请日：2004-04-06

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN ,  VAN BRUNT ROGER

IPC: G06F1/26 ,  G06F1/30 ,  G06F1/32 ,  G06F13/36 ,  G06F13/368 ,  G06F13/38 ,  H04L29/08

CPC classification number: G06F1/325 ,  G06F1/26 ,  G06F1/305 ,  G06F1/32 ,  G06F1/3253 ,  G06F13/36 ,  Y02D10/151

Abstract: PROBLEM TO BE SOLVED: To provide a node for a communication system that has a plurality of ports, each of which may be connected by a point-to-point link.
SOLUTION: The node for the communication system for transmitting signals between the node and a node apart to the communication system has a first bus, a second bus, a repeater for connecting the first bus and the second bus, a transmitter for transferring the signal to a first node apart, a receiver for receiving the signal from the second node apart and a multiplexer circuit. In a first mode, the multiplexer circuit cuts off the transmitter and the receiver from the first and the second buses. In a second mode, the multiplexer circuit selectively connects the transmitter to the first bus so that a signal is transmitted from the first bus and selectively connects the receiver to the second bus to receive the signal.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004056767A

公开(公告)日：2004-02-19

申请号：JP2003140052

申请日：2003-05-19

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN ,  VAN BRUNT ROGER

IPC: G06F3/00 ,  H04L5/14 ,  H04L12/40 ,  H04L25/03 ,  H04L25/38

CPC classification number: H04L5/1423 ,  H04L12/4135

Abstract: PROBLEM TO BE SOLVED: To provide a bus transceiver in which a high speed binary transfer mode for half-duplex binary transfer of data signals is combined with a ternary control transfer mode having a full-duplex dominant logic transmission scheme for full-duplex transfer of control signals. SOLUTION: The transceiver for communications via a transmitting channel has a receiver connected to the transmitting channel, and the receiver receives data according to a binary signal status driven on the transmitting channel from the transmitting channel in the first mode and receives data according to a ternary signal status driven on the transmitting channel from the transmitting channel in the second mode. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种总线收发器，其中数据信号的半双工二进制传输的高速二进制传输模式与具有全双工主导逻辑传输方案的三进制控制传输模式相结合， 控制信号的双工传输。 解决方案：用于经由发送信道进行通信的收发机具有连接到发送信道的接收机，并且接收机根据在第一模式下从发送信道在发送信道上驱动的二进制信号状态接收数据，并且接收数据 涉及在第二模式中从发送信道在发送信道上驱动的三进制信号状态。 版权所有（C）2004，JPO

公开(公告)号：JP2006217639A

公开(公告)日：2006-08-17

申请号：JP2006051939

申请日：2006-02-28

Applicant: Apple Computer Inc ,  アプル・コンピュータ・インコーポレーテッド

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  H04L12/44 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/366 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04L12/64

CPC classification number: H04L12/40078 ,  G06F13/36 ,  G06F13/37 ,  G06F15/17343 ,  H04L12/40084 ,  H04L45/48

Abstract: PROBLEM TO BE SOLVED: To establish communication between nodes in a system where an arbitration assembly of the nodes along a system bus is changed into an acyclic directed graph. SOLUTION: A configuration bus access arbitration system, a priority bus access arbitration system, a token passing bus arbitration system and a preemptive bus initial setting mechanism, etc. are executed. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：建立系统中节点之间的通信，其中沿着系统总线的节点的仲裁组件被改变成非循环有向图。 解决方案：执行配置总线访问仲裁系统，优先总线访问仲裁系统，令牌传递总线仲裁系统和抢占总线初始设置机制等。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002314566A

公开(公告)日：2002-10-25

申请号：JP2002053713

申请日：2002-02-28

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64

Abstract: PROBLEM TO BE SOLVED: To provide a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph and communication between the nodes is established. SOLUTION: The method performs the constituent bus access arbitration system, the preferential bus access arbitration system, the token passing bus arbitration system, and the preemptive bus initialization mechanism or the like.

公开(公告)号：JP2002314565A

公开(公告)日：2002-10-25

申请号：JP2002053699

申请日：2002-02-28

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64

Abstract: PROBLEM TO BE SOLVED: To provide a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph and communication between the nodes is established. SOLUTION: The method performs the constituent bus access arbitration system, the preferential bus access arbitration system, the token passing bus arbitration system, and the preemptive bus initialization mechanism or the like.