公开(公告)号：NO993614D0

公开(公告)日：1999-07-26

申请号：NO993614

申请日：1999-07-26

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  ROSENDALE GLEN A ,  PAYNE JAMES E ,  HANGZO NIANGLAMCHING

IPC: G11C7/10 ,  G11C16/02 ,  G11C

Abstract: A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

公开(公告)号：CA2303234A1

公开(公告)日：1999-06-03

申请号：CA2303234

申请日：1998-11-20

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  ROSENDALE GLEN A ,  PATHAK SAROJ ,  HANGZO NIANGLAMCHING ,  PAYNE JAMES E

IPC: H03K17/22

Abstract: A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).

公开(公告)号：CA2278615A1

公开(公告)日：1999-06-03

申请号：CA2278615

申请日：1998-11-19

Applicant: ATMEL CORP

Inventor： ROSENDALE GLEN A ,  PAYNE JAMES E ,  PATHAK SAROJ ,  HANGZO NIANGLAMCHING

IPC: G11C16/02 ,  G11C7/10 ,  G11C8/00

Abstract: A serial configuration memory device (100) comprises an architecture wherein the reading out of data and the outputting (52) of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme (34 and 44) is provided which allows the first byte to be preloaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.