公开(公告)号：US20160137488A1

公开(公告)日：2016-05-19

申请号：US14543468

申请日：2014-11-17

Applicant: Apple Inc.

Inventor： Tongbi Jiang ,  Jun Zhai

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0048 ,  B81B2207/012 ,  B81C1/00325 ,  B81C2203/0154

Abstract: MEMS packages and modules are described. In an embodiment, a module includes a package mounted within an opening in a module board. The package includes a flexible wiring board mounted to a back surface of the module board and spanning across the opening in the module board. A die is mounted on the flexible wiring board and is encapsulated within an overmold. An air gap exists laterally between the overmold and side surface of the opening in the module board.

Abstract translation: 描述了MEMS封装和模块。 在一个实施例中，模块包括安装在模块板中的开口内的封装。 该封装包括安装到模块板的背面并横跨模块板的开口的柔性布线板。 模具安装在柔性布线板上并被封装在包覆模制中。 在模块板的开口的包覆模制和侧表面之间横向存在气隙。

公开(公告)号：US20150230342A1

公开(公告)日：2015-08-13

申请号：US14244299

申请日：2014-04-03

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H05K3/00 ,  H05K1/11 ,  H05K1/03

CPC classification number: H05K1/115 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/029 ,  H05K2201/09581 ,  Y10T29/49124 ,  H01L2924/00

Abstract: In some embodiments, a carrier substrate for an integrated circuit may include a core, a first plurality of openings, and a first insulating material. The core may include a first surface and a second surface substantially opposing the first surface. The first plurality of openings may extend from the first surface to the second surface of the core. In some embodiments, the first insulating material may be applied to a surface of the first plurality of openings. In some embodiments, the first plurality of openings may include a first conductor extending through each of the first plurality of openings from the first surface to the second surface. In some embodiments, at least a first subset of the first plurality of openings may include a first charge and at least a second subset of the first plurality of openings may include a second charge. The first charge and the second charge may be different.

Abstract translation: 在一些实施例中，用于集成电路的载体衬底可以包括芯，第一多个开口和第一绝缘材料。 芯可以包括基本上与第一表面相对的第一表面和第二表面。 第一多个开口可以从芯的第一表面延伸到第二表面。 在一些实施例中，第一绝缘材料可以施加到第一多个开口的表面。 在一些实施例中，第一多个开口可以包括延伸穿过第一多个开口中的每一个从第一表面到第二表面的第一导体。 在一些实施例中，第一多个开口的至少第一子集可以包括第一电荷，并且第一多个开口的至少第二子集可以包括第二电荷。 第一次充电和第二次充电可能不同。

公开(公告)号：US20250157940A1

公开(公告)日：2025-05-15

申请号：US19021018

申请日：2025-01-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/18

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US20250112154A1

公开(公告)日：2025-04-03

申请号：US18643907

申请日：2024-04-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Antonietta Oliva ,  Sambasivan Narayan ,  Jun Zhai ,  Vidhya Ramachandran ,  Kamal Sikka

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/427 ,  H01L23/473 ,  H01L23/48 ,  H01L23/522

Abstract: Chip structures and electronic modules including a power delivery network (PDN) routing structure and signal routing structure to balance power, signaling, and thermal requirements are described. In an embodiment, the chip includes a device layer, a PDN routing structure on top of the device layer, and a signal routing structure underneath the device layer.

公开(公告)号：US20240321833A1

公开(公告)日：2024-09-26

申请号：US18733580

申请日：2024-06-04

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2224/05009 ,  H01L2225/06513

Abstract: Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.

公开(公告)号：US12087689B2

公开(公告)日：2024-09-10

申请号：US18488561

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/585 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/78 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/30 ,  H01L24/32 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US12074077B2

公开(公告)日：2024-08-27

申请号：US16952567

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Flynn P. Carson ,  Jun Zhai ,  Raymundo M. Camenforte ,  Menglu Li

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/02 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/105 ,  H05K1/0278 ,  H01L23/481 ,  H01L23/5384 ,  H01L2224/24137 ,  H01L2225/06548 ,  H01L2924/18162

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：US20240243012A1

公开(公告)日：2024-07-18

申请号：US18622588

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.

公开(公告)号：US20230402373A1

公开(公告)日：2023-12-14

申请号：US18339132

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/585 ,  H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/08 ,  H01L2224/32145 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/08145

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

公开(公告)号：US20230335440A1

公开(公告)日：2023-10-19

申请号：US18307554

申请日：2023-04-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/17 ,  H01L2924/1427 ,  H01L2924/1436 ,  H01L2924/19042 ,  H01L2924/1432 ,  H01L2924/19103 ,  H01L2224/12105 ,  H01L2224/1703 ,  H01L2924/19104 ,  H01L2224/16265 ,  H01L2924/15192 ,  H01L2224/16235 ,  H01L2924/19041 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2924/1433 ,  H01L2924/18162 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/17181 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.