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    SIGMA-DELTA BASED PHASE LOCK LOOP
    31.
    发明专利
    SIGMA-DELTA BASED PHASE LOCK LOOP 未知

    公开(公告)号：CA2582345A1

    公开(公告)日：2006-04-13

    申请号：CA2582345

    申请日：2005-09-21

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： PARK JOONBAE ,  KOO YIDO ,  AHN YOUNGHO ,  LEE JEONG-WOO ,  SONG EUNSEOK ,  LEE KYEONGHO

    IPC: H03D3/24

    Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

    INTEGRATED CIRCUIT PACKAGE HAVING AN INDUCTANCE LOOP FORMED FROM A MULTI-LOOP CONFIGURATION
    32.
    发明专利
    INTEGRATED CIRCUIT PACKAGE HAVING AN INDUCTANCE LOOP FORMED FROM A MULTI-LOOP CONFIGURATION 未知

    公开(公告)号：CA2537259A1

    公开(公告)日：2005-03-10

    申请号：CA2537259

    申请日：2004-08-27

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： LEE JEONG-WOO ,  KOO YIDO ,  LEE KYEONGHO ,  HUH HYUNGKI ,  LEE KANG YOON ,  PARK JOONBAE

    IPC: H01L29/00 ,  H01L20060101 ,  H01L23/64

    Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/ O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit packag e, a substantial reduction in spacerequirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controll ed by the length of the inductor loop of the package.

    System and method for suppressing noise in a phase-locked loop circuit
    33.
    发明专利
    System and method for suppressing noise in a phase-locked loop circuit 未知

    公开(公告)号：AU2003284893A8

    公开(公告)日：2004-05-25

    申请号：AU2003284893

    申请日：2003-10-23

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： KOO YIDO ,  PARK JOONBAE ,  LEE JEONG-WOO ,  SONG EUNSEOK ,  AHN YOUNGHO ,  LEE KYEONGHO

    IPC: H03L7/197 ,  H03L7/06

    Abstract: A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

    LC OSCILLATOR WITH WIDE TUNING RANGE AND LOW PHASE NOISE
    34.
    发明专利
    LC OSCILLATOR WITH WIDE TUNING RANGE AND LOW PHASE NOISE 未知

    公开(公告)号：CA2488631A1

    公开(公告)日：2003-12-18

    申请号：CA2488631

    申请日：2003-06-05

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： KOO YIDO ,  LEE JEONG-WOO ,  LEE KYEONGHO ,  PARK JOONBAE

    IPC: H03B5/08 ,  H03B1/00 ,  H03B5/12 ,  H03L7/099 ,  H03L7/08

    Abstract: A voltage-controlled oscillator (600) including an active oscillator circuit (610), an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator (600). Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit (610). To avoid damage to the switches in t he capacitive circuits, the capacitive circuits further comprise resistors (622 ). The resistors can be configured in several different ways so that the voltag e- controlled oscillator (600) can have a high degree of reliability, and a wid e tuning range with constant phase noise performance.

    AN ADAPTIVE LINEARIZATION TECHNIQUE FOR COMMUNICATION BUILDING BLOCK
    35.
    发明专利
    AN ADAPTIVE LINEARIZATION TECHNIQUE FOR COMMUNICATION BUILDING BLOCK 未知

    公开(公告)号：CA2458877A1

    公开(公告)日：2003-03-13

    申请号：CA2458877

    申请日：2002-08-29

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： PARK JOONBAE ,  LEE KYEONGHO ,  JEONG HEI-SAM

    IPC: H03F1/32 ,  H03F1/26

    Abstract: The present invention is directed to a linearization apparatus and method. Preferred embodiments according to the present invention can combine an auxiliary non-linear block (300) to a functional block of a system to increa se linearity of an output signal (520) of the system such as a communication system. System overhead due to the non-linear auxiliary block can be small because of circuit structure, cost and low consumption. Further, the non- linear auxiliary block can be designed so that no feedback path is required. Further preferred embodiments can use a feedback path without loss of stability by using a cancellation apparatus or process based on an averaging detection of the output signal. For example, a feedback loop can detect powe r leakage in a sideband caused by non-linearities of the communication system.

    CLOCK GENERATOR AND CLOCK GENERATING METHOD USING DELAY LOCKED LOOP
    36.
    发明申请
    CLOCK GENERATOR AND CLOCK GENERATING METHOD USING DELAY LOCKED LOOP 审中-公开
    使用延迟锁定环的时钟发生器和时钟发生方法

    公开(公告)号：WO2007109225A3

    公开(公告)日：2008-07-24

    申请号：PCT/US2007006800

    申请日：2007-03-16

    Applicant: GCT SEMICONDUCTOR INC ,  PARK JOONBAE ,  LEE KYEONGHO

    Inventor： PARK JOONBAE ,  LEE KYEONGHO

    IPC: H03L7/06 ,  H03L7/16 ,  H03L7/18

    CPC classification number: G06F1/04 ,  H03L7/0816 ,  H03L7/235 ,  H03L2207/10

    Abstract: Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL) In one embodiment, a clock generator can include a first oscillator (XoI) to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop (100) to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider (200) to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second cloc signal, a second oscillator (Xo2) to generate a fourth clock signal and a phase frequency detector (300) to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal

    Abstract translation: 时钟发生器和时钟产生方法的实施例可以使用延迟锁定环（DLL）。在一个实施例中，时钟发生器可以包括第一振荡器（XoI），以产生具有对应于控制信号的频率的第一时钟信号， 延迟锁定环路（100）产生频率高于第一时钟信号的频率的第二时钟信号;分频器（200），用于接收第二时钟信号以产生频率低于第一时钟信号频率的第三时钟信号 产生第四时钟信号的第二振荡器（Xo2）和产生与第三时钟信号和第四时钟信号之间的相位差和/或频率差对应的控制信号的相位频率检测器（300）

    TRANCEIVER CIRCUIT FOR COMPENSATING IQ MISMATCH AND CARRIER LEAKAGE AND METHOD FOR CONTROLLING THE SAME
    37.
    发明申请
    TRANCEIVER CIRCUIT FOR COMPENSATING IQ MISMATCH AND CARRIER LEAKAGE AND METHOD FOR CONTROLLING THE SAME 审中-公开
    用于补偿智能障碍物和载体泄漏的检测器电路及其控制方法

    公开(公告)号：WO2007100678A3

    公开(公告)日：2008-02-07

    申请号：PCT/US2007004755

    申请日：2007-02-22

    Applicant: GCT SEMICONDUCTOR INC ,  PARK JOONBAE ,  LEE KYEONGHO

    Inventor： PARK JOONBAE ,  LEE KYEONGHO

    IPC: H01Q11/12

    CPC classification number: H01Q21/0025

    Abstract: Embodiments of methods, transceiver circuits, and systems can compensate an IQ mismatch (e.g., Tx or Rx) or a carrier leakage using a plurality of local oscillators. One embodiment of a transceiver can include a first up-conversion IQ mixer, a second up-conversion IQ mixer, a first down-conversion IQ mixer with an input to receive an output of the second up-conversion IQ mixer, a second down- conversion IQ mixer with an input to receive an output of the first up-conversion IQ mixer, a first local oscillator to generate a first IQ LO signal for the first up- conversion IQ mixer and the first down-conversion IQ mixer, and a second local oscillator to generate a second IQ LO signal for the second up-conversion IQ mixer and the second down-conversion IQ mixer.

    Abstract translation: 方法，收发器电路和系统的实施例可以使用多个本地振荡器补偿IQ失配（例如，Tx或Rx）或载波泄漏。 收发器的一个实施例可以包括第一上变频IQ混频器，第二上变频IQ混频器，具有用于接收第二上变频IQ混频器的输出的输入的第一下变频IQ混频器， 转换IQ混合器，其具有用于接收第一上变频IQ混频器的输出的输入端，第一本地振荡器，用于产生用于第一上变频IQ混频器和第一下变频IQ混频器的第一IQ LO信号，以及第二本地振荡器 本地振荡器产生用于第二上变频IQ混频器和第二下变频IQ混频器的第二IQ LO信号。

    SERIAL INTERFACE CIRCUIT AND APPARATUS INCLUDING SERIAL INTERFACE CIRCUIT
    39.
    发明申请
    SERIAL INTERFACE CIRCUIT AND APPARATUS INCLUDING SERIAL INTERFACE CIRCUIT 审中-公开
    串行接口电路和包括串行接口电路的设备

    公开(公告)号：WO2007109224A3

    公开(公告)日：2008-07-31

    申请号：PCT/US2007006799

    申请日：2007-03-16

    Applicant: GCT SEMICONDUCTOR INC ,  PARK JOONBAE ,  LEE KYEONGHO

    Inventor： PARK JOONBAE ,  LEE KYEONGHO

    IPC: H03M9/00

    CPC classification number: H03M9/00 ,  H04L25/45

    Abstract: Embodiments include a serial interface circuit, serial interface method and an apparatus including a serial interface circuit. Embodiments of a serial interface circuit can include a frequency divider implemented by using a counter instead of a PLL. One embodiment of a serial interface circuit can include a data receiver to receive first serial data, a serial-parallel converter to convert the first serial data from the data receiver to first parallel data, a clock receiver to receive a first clock signal having a frequency corresponding to the first serial data, and a frequency divider coupled to the clock receiver to generate a second clock signal having a frequency corresponding to the first parallel data with the first clock signal where the frequency divider is configured with a counter.

    Abstract translation: 实施例包括串行接口电路，串行接口方法和包括串行接口电路的装置。 串行接口电路的实施例可以包括通过使用计数器而不是PLL实现的分频器。 串行接口电路的一个实施例可以包括用于接收第一串行数据的数据接收器，将来自数据接收器的第一串行数据转换为第一并行数据的串行 - 并行转换器，用于接收具有频率的第一时钟信号的时钟接收器 对应于第一串行数据，以及分频器，耦合到时钟接收器，以产生具有与第一时钟信号对应的频率的第二时钟信号，其中分频器配置有计数器。

    SIGMA-DELTA BASED PHASE LOCK LOOP
    40.
    发明申请
    SIGMA-DELTA BASED PHASE LOCK LOOP 审中-公开
    基于SIGMA-DELTA的相位锁定环

    公开(公告)号：WO2006039187A3

    公开(公告)日：2007-01-18

    申请号：PCT/US2005034018

    申请日：2005-09-21

    Applicant: GCT SEMICONDUCTOR INC ,  KOO YIDO ,  AHN YOUNGHO ,  SONG EUNSEOK ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

    Inventor： KOO YIDO ,  AHN YOUNGHO ,  SONG EUNSEOK ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

    IPC: H03D3/24

    CPC classification number: H03L7/0895 ,  H03L7/1976

    Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PDF to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

    Abstract translation: 提供了一种基于Σ-Δ的锁相环装置，其包括相位频率检测器（PFD），电荷泵和压控振荡器。 PDF接收参考信号和反馈信号，并且基于参考信号和反馈信号的比较来输出信号。 电荷泵根据PFD的输出信号输出电荷。 电荷泵包括施加固定电流量的第一电流源和第二电流源以施加可变量的电流。 压控振荡器根据来自电荷泵的接收电荷输出时钟信号。

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