公开(公告)号：US20220005952A1

公开(公告)日：2022-01-06

申请号：US16921068

申请日：2020-07-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Wang Zheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure.

公开(公告)号：US11152496B2

公开(公告)日：2021-10-19

申请号：US16776930

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jagar Singh ,  Alexander L. Martin ,  Alexander M. Derrickson

IPC: H01L29/66 ,  H01L29/02 ,  H01L29/08 ,  H01L29/735 ,  H01L29/737 ,  H01L21/8222 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/285 ,  H01L29/45

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

公开(公告)号：US20210175370A1

公开(公告)日：2021-06-10

申请号：US16704002

申请日：2019-12-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Srikanth Balaji Samavedam

IPC: H01L29/872 ,  H01L29/66

Abstract: One illustrative Schottky diode disclosed herein includes a semiconductor substrate, an anode region and a cathode region. The anode region includes a plurality of first fins with a first vertical height formed in the anode region, wherein an upper surface of the semiconductor substrate is exposed within the anode region. The cathode region includes a plurality of second fins with a second vertical height that is greater than the first vertical height. The device also includes a conductive structure that contacts and engages at least an upper surface of the plurality of first fins in the anode region.

公开(公告)号：US12295161B2

公开(公告)日：2025-05-06

申请号：US17582550

申请日：2022-01-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Rong-Ting Liou ,  Man Gu ,  Jeffrey B. Johnson ,  Wang Zheng ,  Jagar Singh ,  Haiting Wang

IPC: H10D62/10 ,  H01L21/762 ,  H10D30/01 ,  H10D30/65

Abstract: An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.

公开(公告)号：US11967637B2

公开(公告)日：2024-04-23

申请号：US17687741

申请日：2022-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ali Razavieh ,  Jagar Singh ,  Haiting Wang

IPC: H01L29/735 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/73 ,  H01L29/737 ,  H01L29/78

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/7302 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/737 ,  H01L29/785

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

公开(公告)号：US11935923B2

公开(公告)日：2024-03-19

申请号：US17525256

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Vibhor Jain ,  Judson R. Holt ,  Jagar Singh ,  Mankyu Yang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/735 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

公开(公告)号：US20240030343A1

公开(公告)日：2024-01-25

申请号：US17814611

申请日：2022-07-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Saloni Chaurasia ,  Man Gu ,  Jagar Singh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/51

CPC classification number: H01L29/7835 ,  H01L29/0847 ,  H01L29/517

Abstract: A transistor structure includes a semiconductor substrate with a source region and a drain region therein that are asymmetric. A gate dielectric structure includes a first gate oxide region over a portion of the source region, a second gate oxide region over a portion of the drain region, and a high dielectric constant (high-K) dielectric layer contacting the semiconductor substrate and separating the first gate oxide region from the second gate oxide region. A gate body is over the gate dielectric structure.

公开(公告)号：US11843034B2

公开(公告)日：2023-12-12

申请号：US17529002

申请日：2021-11-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Haiting Wang ,  Jagar Singh

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L29/423

CPC classification number: H01L29/1008 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/735

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.

公开(公告)号：US11721722B2

公开(公告)日：2023-08-08

申请号：US17524438

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Man Gu ,  Jagar Singh ,  Haiting Wang ,  Jeffrey Johnson

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/735 ,  H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1008 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7842

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

公开(公告)号：US20230063301A1

公开(公告)日：2023-03-02

申请号：US17557176

申请日：2021-12-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Arkadiusz Malinowski ,  Jagar Singh ,  Mankyu Yang ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region