公开(公告)号：PT94400A

公开(公告)日：1992-02-28

申请号：PT9440090

申请日：1990-06-18

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F15/00 ,  G06F1/04 ,  G06F1/12 ,  G06F1/24 ,  G06F

Abstract: A microprocessor based computer system is provided which includes a reset circuit having a phase error detector for detecting a phase error between an initial reset signal and a clock signal provided to the microprocessor clock input. The reset circuit further includes a phase error corrector for adjusting the phase of the clock signal if a phase error is detected so as to substantially minimize the phase error. The reset circuit includes a reset signal regenerator for providing a new reset signal to the reset input of the microprocessor when the phase of the clock signal is adjusted.

公开(公告)号：AU616604B2

公开(公告)日：1991-10-31

申请号：AU5506690

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：IT8920625D0

公开(公告)日：1989-05-24

申请号：IT2062589

申请日：1989-05-24

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：DE69031768D1

公开(公告)日：1998-01-15

申请号：DE69031768

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：AT160890T

公开(公告)日：1997-12-15

申请号：AT90305297

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：SG42806A1

公开(公告)日：1997-10-17

申请号：SG1995002115

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：CA2016400C

公开(公告)日：1996-01-02

申请号：CA2016400

申请日：1990-05-09

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08 ,  G06F12/00 ,  G06F13/16

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：CA2016401C

公开(公告)日：1994-01-11

申请号：CA2016401

申请日：1990-05-09

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F15/00 ,  G06F1/04 ,  G06F1/12 ,  G06F1/24

Abstract: A microprocessor based computer system is provided which includes a reset circuit having a phase error detector for detecting a phase error between an initial reset signal and a clock signal provided to the microprocessor clock input. The reset circuit further includes a phase error corrector for adjusting the phase of the clock signal if a phase error is detected so as to substantially minimize the phase error. The reset circuit includes a reset signal regenerator for providing a new reset signal to the reset input of the microprocessor when the phase of the clock signal is adjusted.

公开(公告)号：AU625084B2

公开(公告)日：1992-07-02

申请号：AU5571490

申请日：1990-05-18

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F13/36 ,  G06F12/00 ,  G06F12/02 ,  G06F13/28 ,  G06F13/42 ,  G06F13/38

Abstract: A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode.

公开(公告)号：BR9002876A

公开(公告)日：1991-08-20

申请号：BR9002876

申请日：1990-06-18

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F9/00

Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.