公开(公告)号：DE112004000745T5

公开(公告)日：2006-06-08

申请号：DE112004000745

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  LI YUJUN ,  MOUMEN NAIM ,  WRSCHKA PORSHIA SHANE

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/265 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

公开(公告)号：DE69930894D1

公开(公告)日：2006-05-24

申请号：DE69930894

申请日：1999-06-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  TOSHIBA KAWASAKI KK

Inventor： RENGARAJAN RAJESH ,  SRINIVASAN RADHIKA ,  INOUE HIROFUMI ,  BEINTNER JOCHEN

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/08

Abstract: A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.

公开(公告)号：DE60103398T2

公开(公告)日：2005-06-09

申请号：DE60103398

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LEE GILL YONG ,  HALLE SCOTT D ,  BEINTNER JOCHEN

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/311 ,  H01L21/314 ,  H01L21/8242

Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

公开(公告)号：DE10354717A1

公开(公告)日：2004-07-15

申请号：DE10354717

申请日：2003-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  ECONOMIKOS LAERTIS ,  KNORR ANDREAS ,  WISE MICHAEL L

IPC: H01L21/304 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242

Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.