公开(公告)号：CA2071333C

公开(公告)日：1996-09-10

申请号：CA2071333

申请日：1992-06-16

Applicant: IBM

Inventor： CARMON DONALD E ,  CROUSE WILLIAM G

IPC: G06F3/06 ,  G06F3/08 ,  G06F5/10 ,  G06F13/38 ,  G06F13/42 ,  G11B20/10 ,  G06F13/10 ,  G11B27/10 ,  G06F1/12

Abstract: A method and apparatus for controlling the readout rate of information from a sequential storage medium, such as a CD-ROM, to maintain synchronism between the device containing the medium and an independent receiver receiving the information. Information is loaded from the media into a buffer at a rate controlled by pulses from a device clock. Information is unloaded from the buffer for utilization by the receiver independently of the loading of the buffer. The amount of free space available in the buffer is measured as information is loaded into the buffer. The rate of the clock is dynamically adjusted in response to the amount of free buffer space to maintain the full state of the buffer within predetermined limits. In this manner, the buffer never empties or fills in response to the unloading by the independent receiver.

公开(公告)号：BR9203427A

公开(公告)日：1993-04-20

申请号：BR9203427

申请日：1992-09-02

Applicant: IBM

Inventor： CARMON DONALD E ,  CROUSE WILLIAM G ,  WARE MALCOLM S

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F13/14

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：CA2069711A1

公开(公告)日：1993-03-19

申请号：CA2069711

申请日：1992-05-27

Applicant: IBM

Inventor： CARMON DONALD E ,  CROUSE WILLIAM G ,  WARE MALCOLM S

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：CA1201541A

公开(公告)日：1986-03-04

申请号：CA435246

申请日：1983-08-24

Applicant: IBM

Inventor： CROUSE WILLIAM G ,  IRVIN DAVID R

IPC: H04B3/20 ,  H04B3/21 ,  H04M3/18

Abstract: ADAPTIVE SUB-BAND ECHO SUPPRESSOR The subject suppressor is an improved form of echo suppressor used in conjunction with adaptive sub-band speech coders. The suppressor analyzes and uses N contiguous sub-bands of a sub-band speech coder. The intermediate results calculated during the normal operation of such speech coders may be analyzed in the suppressor to determine predictions for the echo levels of each sub-band and to set break in and break out thresholds. A substantial performance improvement with little increase in complexity over current echo suppressors is achieved. The subject suppressor may also be used with adaptive transform speech coders in which the corner frequency points define the edges of "sub-bands" for purposes of this invention. Sub-bands are defined here as contiguous segments of the frequecy-energy spectrum. The sub-bands so defined can be formed or analytically divided by a bank of filters as in normal sub-band coders or they can be identified or analyzed as noted above by the corner points of an adaptive transform coder.

公开(公告)号：FR2363235A1

公开(公告)日：1978-03-24

申请号：FR7720046

申请日：1977-06-21

Applicant: IBM

Inventor： CROUSE WILLIAM G

IPC: H03M1/82 ,  H03M1/00 ,  H03K13/02

公开(公告)号：CA839956A

公开(公告)日：1970-04-21

申请号：CA839956D

Applicant: IBM

Inventor： CROUSE WILLIAM G

公开(公告)号：CA830087A

公开(公告)日：1969-12-16

申请号：CA830087D

Applicant: IBM

Inventor： CROUSE WILLIAM G

公开(公告)号：CA811843A

公开(公告)日：1969-04-29

申请号：CA811843D

Applicant: IBM

Inventor： CROUSE WILLIAM G