公开(公告)号：JP2007184583A

公开(公告)日：2007-07-19

申请号：JP2006343524

申请日：2006-12-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VIJAY NARAYANAN ,  VAMSI K PARUCHURI ,  CHEN TZE-CHIANG ,  ALESSANDRO CALLEGARI ,  JOSEPH S NEWBURY ,  MICHELLE L STEEN ,  DORIS BRUCE B ,  MICHAEL PATRIK CHUDZIK ,  LINDER BARRY P ,  JOHN C ARNOLD

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS circuit which includes an n-FET gate stack having a gate dielectric and a metal gate conductor, and a p-FET gate stack having a gate dielectric layer and a silicon-containing gate conductor. SOLUTION: In the high-performance complementary metal oxide film semiconductor (CMOS) circuit, each semiconductor unit has at least the first gate stack and the second gate stack. The first gate stack is disposed on a first device region (e.g., n-FET device region) in a semiconductor board, and at least includes a gate dielectric layer 14, a metal gate conductor 16, and a silicon-containing gate conductor 18 that are laminated in increasing order. The second gate stack is disposed on a second device region (e.g., p-FET device region) in the semiconductor board; and at least includes a gate dielectric layer, and a silicon-containing gate conductor that are laminated in increasing order. The first and second gate stacks can be formed on the semiconductor board by a variety of integrated methods. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种CMOS电路，其包括具有栅极电介质和金属栅极导体的n-FET栅极堆叠，以及具有栅极介电层和含硅栅极导体的p-FET栅极堆叠 。 解决方案：在高性能互补金属氧化物半导体（CMOS）电路中，每个半导体单元至少具有第一栅极堆叠和第二栅极堆叠。 第一栅极堆叠设置在半导体板中的第一器件区域（例如，n-FET器件区域）上，并且至少包括栅极电介质层14，金属栅极导体16和含硅栅极导体18， 以增加的顺序层压。 第二栅极堆叠设置在半导体板中的第二器件区域（例如，p-FET器件区域）上; 并且至少包括以增加的顺序层叠的栅极介电层和含硅栅极导体。 第一和第二栅极堆叠可以通过各种集成方法形成在半导体板上。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005197734A

公开(公告)日：2005-07-21

申请号：JP2005000206

申请日：2005-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEVEN W ,  DORIS BRUCE B ,  ZHANG YING ,  ZHU HUILONG

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device, realizing a strained Si film with reduced number of defects.
SOLUTION: The strained Si film is formed by selectively growing a fin arranged in a perpendicular direction to the surface of a non-conductive substrate or Si on the side face of a relaxed SiGe block. Next, a dielectric gate comprising an oxide or a high k material or a combination thereof, for example, can be formed on the surface of the strained Si film. Further, by removing the relaxed SiGe block without substantially influencing the stress of the strained Si film, a second gate oxide can be formed on the surface previously occupied by the relaxed SiGe block. Thus, a MOSFET and a finFET of a single gate, double gate, or more gates can be formed, with the semiconductor device having the strained Si fin arranged in the perpendicular direction on the non-conductive substrate, with a channel having reduced number of defects or reduced dimension or both.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种方法和装置，实现了具有减少的缺陷数量的应变Si膜。 解决方案：通过选择性地生长沿垂直于非导电衬底的表面布置的翅片或在弛豫的SiGe块的侧面上的Si来形成应变Si膜。 接下来，可以在应变Si膜的表面上形成例如包含氧化物或高k材料或其组合的电介质栅。 此外，通过去除弛豫的SiGe块而基本上不影响应变的Si膜的应力，可以在松弛的SiGe块以前占据的表面上形成第二栅极氧化物。 因此，可以形成单栅极，双栅极或更多栅极的MOSFET和finFET，其中半导体器件具有沿非垂直方向布置在非导电衬底上的应变Si鳍，沟道具有减少的数量 缺陷或尺寸减小或两者兼有。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214631A

公开(公告)日：2004-07-29

申请号：JP2003400729

申请日：2003-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  GLUSCHENKOV OLEG ,  BELYANKSY MICHAEL ,  DORIS BRUCE B

IPC: H01J1/312 ,  H01L21/00 ,  H01L21/033 ,  H01L21/205 ,  H01L21/425 ,  H01L29/06 ,  H01L29/76 ,  H01L31/0336 ,  H01L31/0352

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/0337 ,  H01L31/0352

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a uniform layer structure, including an ultra-thin layer of amorphous silicon and a thermal oxide thereof. SOLUTION: In one side surface, the present invention is a method for forming the nano-laminate of an oxidized silicon on a substrate. In the other side surface, the invention is a method for forming a patterned hard mask on the substrate. The patterned hard mask includes the nano-laminate of a silicon and the oxidized silicon. The methods are characterized by the oxidization of an amorphous silicon layer using atomic oxygen. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2010192919A

公开(公告)日：2010-09-02

申请号：JP2010091082

申请日：2010-04-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B

IPC: H01L21/76 ,  H01L21/301 ,  H01L21/311 ,  H01L21/318 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

Abstract: PROBLEM TO BE SOLVED: To provide a method for protecting shallow trench isolation (STI) during an oxide etching process. SOLUTION: This method for protecting the semiconductor shallow trench isolation (STI) oxide 4 from the etching comprises: a step of, if necessary, making the top face of the STI oxide 4 lower than the top face of an adjacent silicon activated region 3; a step of depositing a nitride liner 5 on the STI oxide 4 and the adjacent silicon activated region 3 by a method effective for delimiting a concave portion above the STI oxide 4; a step of filling the concave portion with a protecting film 6; and a step of removing the nitride liner from the adjacent activated region. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在氧化物蚀刻工艺期间保护浅沟槽隔离（STI）的方法。 解决方案：用于从蚀刻保护半导体浅沟槽隔离（STI）氧化物4的方法包括：如果需要，使STI氧化物4的顶面低于相邻硅活化的顶面的步骤 区域3; 通过有效地限定STI氧化物4上方的凹部的方法，在氮化硅衬垫5和相邻硅活化区3上淀积氮化物衬垫5的工序; 用保护膜6填充凹部的步骤; 以及从相邻的活化区域去除氮化物衬垫的步骤。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007184584A

公开(公告)日：2007-07-19

申请号：JP2006343832

申请日：2006-12-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN TZE-CHIANG ,  DORIS BRUCE B ,  VAMSI K PARUCHURI ,  MICHAEL PATRIK CHUDZIK ,  VIJAY NARAYANAN ,  MICHELLE L STEEN ,  ALESSANDRO CALLEGARI ,  KIM YOUNG-HEE ,  ZHANG YING

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823857 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To prevent the depletion of the gate polysilicon of a CMOS by a gate electrode structure composed of a metal dielectric stack containing a large volume of potassium. SOLUTION: A semiconductor structure is provided by including an n-FET device and a p-FET device. At least either of the devices includes a gate electrode stack having a thin film of a silicon-containing electrode, i.e., polysilicon electrode and a first metal on the silicon-containing electrode. The other of the devices includes a gate electrode stack not having a thin film of a silicon-containing electrode but at least having a first metal gate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过由含有大量钾的金属电介质堆叠构成的栅电极结构来防止CMOS的栅极多晶硅的耗尽。 解决方案：通过包括n-FET器件和p-FET器件来提供半导体结构。 所述器件中的至少一个包括具有含硅电极的薄膜的栅电极堆叠，即多晶硅电极和含硅电极上的第一金属。 另一个器件包括不具有含硅电极薄膜但至少具有第一金属栅极的栅极电极堆叠。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005217400A

公开(公告)日：2005-08-11

申请号：JP2005011467

申请日：2005-01-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  DORIS BRUCE B ,  GHALI ROMANY ,  GLUSCHENKOV OLEG G ,  GRIBELYUK MICHAEL A ,  LEE WOO-HYEONG ,  MADAN ANITA

IPC: C23C16/24 ,  C23C16/46 ,  H01L21/00 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: C23C16/24 ,  C23C16/46 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a polycrystalline silicon having hyperfine particle sizes.
SOLUTION: The method of forming a polycrystalline silicon having hyperfine particle sizes employs a differential heating of upper and lower surfaces of a substrate of a CVD apparatus, in which the lower surface of the substrate receives considerably more power than the upper surface, preferably more than 75% of the entire power; and in which the substrate is maintained during deposition at a temperature higher than 50°C above 550°C of crystallization temperature of silicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 待解决的问题：提供一种形成具有超细粒径的多晶硅的方法。 解决方案：形成具有超细粒度的多晶硅的方法采用CVD装置的基板的上表面和下表面的差加热，其中基板的下表面比上表面受到相当大的功率， 优选超过整个功率的75％; 并且其中在高于硅的结晶温度高于550℃的温度高于50℃的温度下沉积时，保持基板。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004207705A

公开(公告)日：2004-07-22

申请号：JP2003409571

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B ,  HEGDE SURYANARAYAN G ,  IEONG MEIKEI ,  JONES ERIN C

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/337 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

CPC classification number: H01L29/66916 ,  H01L29/42316 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/802

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a double-gate type field effect transistor (DGFET) of a self-aligning planar type with a front gate and a back gate aligned.
SOLUTION: A method of manufacturing this double-gate type field effect transistor (DGFET) comprises: a process of preparing a stacked double-gate structure provided with at least a back gate 14, a back gate dielectric provided on the back gate 14, a channel layer provided on the back gate dielectric, a front gate dielectric provided on the channel layer, and a front gate 22 provided on the front gate dielectric; a process of patterning the front gate 22 of the stacked double-gate structure; a process of forming a sidewall spacer on the exposed sidewall of the pattered front gate 22; and a process of forming a carrier depletion zone at a part of the back gate and allowing the carrier depletion zone to align the back gate to the front gate.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2014172159A8

公开(公告)日：2014-11-13

申请号：PCT/US2014033477

申请日：2014-04-09

Applicant: IBM ,  ST MICROELECTRONICS INC ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CHENG KANGGUO ,  DORIS BRUCE B ,  GRENOUILLET LAURENT ,  KHAKIFIROOZ ALI ,  LE TIEC YANNICK ,  LIU QING ,  VINET MAUD

IPC: H01L21/761 ,  H01L29/06

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming (304) a well in a semiconductor substrate. A pocket is formed (306) within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created (310) at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成（304）阱。 在阱内形成口袋（306），该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷（310），使得p-n结的漏电阻降低。

公开(公告)号：WO2009100053A2

公开(公告)日：2009-08-13

申请号：PCT/US2009032936

申请日：2009-02-03

Applicant: IBM ,  BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

Inventor： BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

IPC: H01L21/20

CPC classification number: H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

Abstract: In one embodiment, hexagonal tiles encompassing a large are divided into three groups, each containing one-third of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group (01, 02, 03) are formed in a template layer (2OA, 2OB, 20C), and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self- aligned line and space structures (4OA, 5OA; 4OB, 5OB; 4OC, 50C) are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

Abstract translation: 在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的三分之一。 每个组（01,02,03）中的六边形瓦片的开口形成在模板层（20A，20B，20C）中，并且在每个开口内施加和组合一组自组装嵌段共聚物。 该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。 在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。 每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。 在每组中以顺序的方式形成自组装自对准线和空间结构（40A，50A; 40B，50B; 40C，50C），使得线和空间图形形成在延伸超过 订购。

公开(公告)号：WO2005050701A8

公开(公告)日：2005-11-03

申请号：PCT/US2004037434

申请日：2004-11-09

Applicant: IBM ,  DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L21/8238 ,  H01L31/119 ,  H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L31/113

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Abstract translation: 一种制造半导体器件结构的方法，包括：提供衬底（1），在所述衬底（1）上提供电极（6），在所述电极（6）中形成凹部（12），所述凹部具有开口， 在凹部内设置小晶粒半导体材料（17），在凹部内覆盖开口以容纳小晶粒半导体材料，然后对所得结构进行退火。