公开(公告)号：DE60233872D1

公开(公告)日：2009-11-12

申请号：DE60233872

申请日：2002-05-30

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MA WILLIAM

IPC: H01L21/76 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack.

公开(公告)号：AT444567T

公开(公告)日：2009-10-15

申请号：AT02735604

申请日：2002-05-30

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MA WILLIAM

IPC: H01L21/76 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack.