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    AN INTERMEDIATE MANUFACTURE FOR A DUAL GATE LOGIC DEVICE
    1.
    发明申请
    AN INTERMEDIATE MANUFACTURE FOR A DUAL GATE LOGIC DEVICE 审中-公开
    双门逻辑器件的中间制造

    公开(公告)号：WO02101834A3

    公开(公告)日：2003-05-30

    申请号：PCT/GB0202622

    申请日：2002-05-30

    Applicant: IBM ,  IBM UK

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MA WILLIAM

    IPC: H01L21/76 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49

    CPC classification number: H01L29/66484 ,  H01L21/2807 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648

    Abstract: The present invention features double-or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.

    Abstract translation: 本发明的特征在于双栅极或双栅极逻辑器件，其包含始终自对准并且具有恒定宽度的沟道的栅极导体。 本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。 以这种方式，可以将栅极导体封装在介电壳中，而不改变硅沟道的长度。 采用单晶硅晶片作为通道材料。 自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。 通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。 描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。

    2.
    发明专利
    未知

    公开(公告)号：AT438926T

    公开(公告)日：2009-08-15

    申请号：AT02796462

    申请日：2002-08-29

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  LEAS JAMES ,  MA WILLIAM ,  RABIDOUX PAUL

    IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

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