公开(公告)号：FR2282675A1

公开(公告)日：1976-03-19

申请号：FR7518985

申请日：1975-06-09

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HSIAO MU-YUE ,  PATEL ARVIND M

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/00

Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.

公开(公告)号：CA935932A

公开(公告)日：1973-10-23

申请号：CA106344

申请日：1971-02-26

Applicant: IBM

Inventor： HSIAO MU-YUE ,  BOSSEN D

IPC: H03M13/43

Abstract: A multiple error correcting system for correcting t (t 2) errors in message of k data bits, m2 k (m+1)2, where m is an integer of at least three, comprises encoding means and decoding means. The encoding means adds r check bits, each check bit corresponding to a number of data bits; each data bit is represented by 2t check bits; these 2t check bits have only the one data bit in common; and, the number, r, of check bits is: 2mt r 2(m+1)t. The decoding means for each data bit has an error correcting circuit receiving 2t+1 inputs from input circuitry, the inputs being the data bit itself, and 2t combinations of check bits and other data bits representing the data bit. The error correcting circuit is capable of producing an output signal correctly corresponding to a data bit if no more than t inputs thereto for that data bit were in error. A coding system for generating these r check bits by augmenting Latin square codes is described.

公开(公告)号：CA935930A

公开(公告)日：1973-10-23

申请号：CA71348

申请日：1970-01-05

Applicant: IBM ,  CHIEN R

Inventor： CHIEN R ,  HSIAO MU-YUE ,  SELLERS F JR ,  BOSSEN D

IPC: H03M13/19 ,  H04L1/00

Abstract: 1,247,823. Error-correcting systems. INTERNATIONAL BUSINESS MACHINES CORP., and ROBERT TIENWEN CHIEN. 8 Jan., 1970 [8 Jan., 1969], No. 1041/70. Heading G4A. A message containing k data bits has 2m check bits added to it (k#m 2 , where m=integer greater than 1) for each of t error-correcting capabilities (t#1), and a decoder comprises t parity-checking circuits supplying outputs to an error-correcting circuit for that bit. As an example, where k=25 and m=5, the message bits d 0 -d 24 are considered arranged as a 5 x 5 matrix, check bits c 1 -c 5 are derived by exclusive OR operation on the matrix rows (e.g. c 1 =EXOR (do, d 1 , d 2 , d 3 , d 4 ) and check bits c 6 -c 10 are similarly derived from the matrix columns (e.g. c 6 =EXOR d 0 , d 5 , d 10 , d 15 , d 20 ) to provide for single error correction. For each additional error correction capability, a pair of orthogonal Latin squares such as L 1 , L 2 and L 3 , L 4 , Fig. 4, is used to select two groups of 5 bits from the matrix, each group comprising bits located in positions marked with the same number in the Latin squares, the additional check bits c 11 -c 15 (L 1 ), C 16 -C 20 (L 2 ) again being derived by exclusive OR operation on the 5 selected bits. Each bit d 0 -d 24 therefore occurs in only two of the equations defining each set of mt check bits. For each bit, such as d 0 , the error-correcting decoder comprises a module I-III, Fig. 5, for each error-correcting capability, each module consisting of a pair of exclusive OR circuits such as 30, 32 receiving inputs corresponding to the check bit equations in which that bit occurs, e.g. for do circuit 30 has inputs d 1 -d 4 and c 1 . Each circuit 30, 32 provides an output which should be a copy of the corresponding bit, and these copies, together with the original bit are supplied to a majority logic gate 38 to provide a corrected output, assuming not more than the number of random errors allowed for have occurred. For the ease where k

公开(公告)号：GB1287238A

公开(公告)日：1972-08-31

申请号：GB1710371

申请日：1971-05-26

Applicant: IBM

Inventor： HSIAO MU-YUE ,  MIKHAIL WADIE F

IPC: H03M13/13

Abstract: 1287238 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 26 May 1971 [23 Oct 1970] 17103/71 Heading G4A A register 10 storing a word including check and data bits (e.g. in a Bose-Chaudhuri code) is connected to a syndrome generator 31 (an EX-OR tree), a decoder 33 responds to a syndrome pattern representing a single error to correct the erroneous bit in register 10, and control circuits 34 connected to the syndrome generator 31 and the decoder 33 respond to a syndrome pattern representing a double error to change the bits in register 10 one by one until one of the two errors present is corrected, any changed bit which does not correct an error being restored back to the original bit, whereupon the decoder responds to the new syndrome pattern to correct the remaining single error. The bits in register 10 may be successively complemented by a shift register holding a single 1 which is stepped along one stage for each test operation and, after the first stage of register 10, complements two adjacent stages to change one bit and restore the preceding, already tested, bit. Control circuits 34 include gates which besides detecting double errors to initiate correction also allow higher order errors to be detected.