公开(公告)号：US3685014A

公开(公告)日：1972-08-15

申请号：US3685014D

申请日：1970-10-09

Applicant: IBM

Inventor： HSIAO MY-YUE ,  MIKHAIL WADIE F

IPC: H03M13/15 ,  G06F11/12 ,  G08C25/00

CPC classification number: H03M13/15

Abstract: A method and apparatus are provided for detecting and correcting double errors and detecting triple errors by generating syndrome S bits from check bits and data bits of a binary word. The syndrome S bits themselves are decoded to locate and correct single errors. Code bit combinations h1, h2,-hn which indicate the location of the single errors are compared with the syndrome S bits by successive half add operations to produce successive results R1, R2,-Rn. If double errors occur in the binary word, the syndrome S bits reflect the double error by the relationship S hi V hj. When i compare or half add operations are performed, the result Ri yields a discrete combination of code bits which indicates the location of one of the double errors because Rx S V hi hj. Then hj is decoded to correct one of the double errors. When one of the double errors is corrected, a new set of syndrome S bits is generated, and this yields S hi. The syndrome S bits are decoded next to correct the second error in the binary word. Thus double errors occurring in bits i and j of the binary word are detected and corrected.

Abstract translation: 提供了一种用于检测和校正双重错误并通过从二进制字的校验位和数据位产生校正子S位来检测三重误差的方法和装置。 综合征S位本身被解码以定位和纠正单个错误。 指示单个错误的位置的代码组合h1，h2，-hn通过连续的半加运算与校正子S比较，以产生连续的结果R1，R2，-Rn。 如果在二进制字中出现双重错误，则校正子S比特通过关系S = hi V hj反映双重误差。 当进行比较或半加运算时，结果Ri产生代码位的离散组合，其指示双误差之一的位置，因为Rx = S V hi = hj。 然后hj被解码以纠正一个双重错误。 当其中一个双重错误被纠正时，产生一组新的综合征S比特，这产生S = hi。 下一个解码校正器S位被解码，以校正二进制字中的第二个错误。 因此，检测并纠正在二进制字的位i和j中出现的双重误差。

公开(公告)号：US3656107A

公开(公告)日：1972-04-11

申请号：US3656107D

申请日：1970-10-23

Applicant: IBM

Inventor： HSIAO MU-YUE ,  MIKHAIL WADIE F

IPC: H03M13/13 ,  G08C25/00

CPC classification number: H03M13/13

Abstract: A method and apparatus are provided for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits. The syndrome S bits themselves are decoded to locate and correct single errors. Wen double errors occur in the binary word, the syndrome S bits automatically operate a switching device which changes the bits of the binary word one at a time to correct one of the double errors. If one of the double errors is not corrected when a given bit is changed, this is indicated by the syndrome S bits, and the bit under test is restored as the next bit of the binary word is changed or complemented. Whenever one of the double errors is corrected by the switching device, the syndrome bits then indicate the location of the remaining single error, and the syndrome S bits are decoded to correct the second one of the double errors.

Abstract translation: 提供了一种通过从具有校验位和数据位的二进制字中产生校正子S位来自动检测和校正双重误差的方法和装置。 综合征S位本身被解码以定位和纠正单个错误。 文双字错误出现在二进制字中，综合征S位自动操作一个切换装置，它一次更改一个二进制字的位，以纠正一个双重错误。 当给定位改变时，如果双精度错误中的一个未被纠正，则由校验位S位指示，并且当二进制字的下一位被改变或补充时，被测位被恢复。 无论何时一个双重错误由开关装置校正，则校正子位然后指示剩余的单个错误的位置，并且校正子S位被解码以校正第二个双重错误。

公开(公告)号：CA969666A

公开(公告)日：1975-06-17

申请号：CA125321

申请日：1971-10-18

Applicant: IBM

Inventor： HSIAO MU-YUE ,  MIKHAIL WADIE F

IPC: H03M13/13 ,  G06F11/08

Abstract: A method and apparatus are provided for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits. The syndrome S bits themselves are decoded to locate and correct single errors. Wen double errors occur in the binary word, the syndrome S bits automatically operate a switching device which changes the bits of the binary word one at a time to correct one of the double errors. If one of the double errors is not corrected when a given bit is changed, this is indicated by the syndrome S bits, and the bit under test is restored as the next bit of the binary word is changed or complemented. Whenever one of the double errors is corrected by the switching device, the syndrome bits then indicate the location of the remaining single error, and the syndrome S bits are decoded to correct the second one of the double errors.

公开(公告)号：FR2337426A1

公开(公告)日：1977-07-29

申请号：FR7635301

申请日：1976-11-19

Applicant: IBM

Inventor： BALYOZ JOHN ,  GRUODIS ALGIRDAS J ,  JEN TEH-SEN ,  MIKHAIL WADIE F

IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L21/72 ,  H01L27/04

Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

公开(公告)号：CA1064624A

公开(公告)日：1979-10-16

申请号：CA268098

申请日：1976-12-17

Applicant: IBM

Inventor： BALYOZ JOHN ,  GRUODIS ALGIRDAS J ,  JEN TEH-SEN ,  MIKHAIL WADIE F

IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52

Abstract: HIGH DENSITY SEMICONDUCTOR CIRCUIT LAYOUT An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

公开(公告)号：GB1287238A

公开(公告)日：1972-08-31

申请号：GB1710371

申请日：1971-05-26

Applicant: IBM

Inventor： HSIAO MU-YUE ,  MIKHAIL WADIE F

IPC: H03M13/13

Abstract: 1287238 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 26 May 1971 [23 Oct 1970] 17103/71 Heading G4A A register 10 storing a word including check and data bits (e.g. in a Bose-Chaudhuri code) is connected to a syndrome generator 31 (an EX-OR tree), a decoder 33 responds to a syndrome pattern representing a single error to correct the erroneous bit in register 10, and control circuits 34 connected to the syndrome generator 31 and the decoder 33 respond to a syndrome pattern representing a double error to change the bits in register 10 one by one until one of the two errors present is corrected, any changed bit which does not correct an error being restored back to the original bit, whereupon the decoder responds to the new syndrome pattern to correct the remaining single error. The bits in register 10 may be successively complemented by a shift register holding a single 1 which is stepped along one stage for each test operation and, after the first stage of register 10, complements two adjacent stages to change one bit and restore the preceding, already tested, bit. Control circuits 34 include gates which besides detecting double errors to initiate correction also allow higher order errors to be detected.