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公开(公告)号：US3703705A
公开(公告)日：1972-11-21
申请号：US3703705D
申请日：1970-12-31
Applicant: IBM
Inventor： PATEL ARVIND M
CPC classification number: H03M13/15
Abstract: A linear feedback shift register for operating on a plurality f of parallel inputs according to a generator polynomial to produce encoding and decoding is provided having a plurality r of shift register stages X0 . . . Xr 1 each corresponding to one of the terms in the generator polynomial. A first plurality of modulo 2 addition means connect, for modulo 2 addition, each of said f data bit inputs Zt f 1, Zt f 2, . . . , Zt 1, Zt of the shift register to the output of an individual one of the last f register stages Xr f, Xr f 1, . . . , Xr 1 according to the relationship Zt f 1 to Xr f, Zt f 2 to Xr f 1, . . . , Zt to Xr 1. A second plurality of modulo 2 addition means are connected to the respective inputs of the first Xr f 2 shift register stages. The first feedback connection from the output of each of said first plurality of modulo 2 addition means in said f shift register stages is connected to each of two preceding second modulo 2 addition means in accordance with the relationship Xr f 1 to X1 and X2; Xr f 2 to X2 and X3; Xr 1 to Xr f 1 and Xr f 2. A third modulo 2 addition means connects each output of the first plurality of modulo 2 addition means to the register stages determined in accordance with the non-zero coefficients in the generator polynomial.
Abstract translation: 提供一种线性反馈移位寄存器，用于根据生成多项式在并行输入的多个f上操作以产生编码和解码，其具有多个移位寄存器级X0。 。 。 Xr-1各自对应于生成多项式中的一个项。 第一多个模2加法装置连接，用于模2加法，每个所述f数据比特输入Zt + f-1，Zt + f-2。 。 。 ，Zt + 1，Zt到最后f个寄存器级Xr-f，Xr-f + 1中的一个的输出。 。 。 ，Xr-1，根据关系Zt + f-1〜Xr-f，Zt + f-2〜Xr-f + 1。 。 。 Zt到Xr-1。 第二组多个模2加法装置连接到第一Xr-f + 2移位寄存器级的相应输入端。 根据Xr-f + 1至X1和X2的关系，将所述f个移位寄存器级中的所述第一多模2加法装置的每一个的输出的第一反馈连接连接到前两个第二模2加法装置中的每一个 ; Xr-f + 2〜X2和X3; Xr-1至Xr-f + 1和Xr-f + 2。 第三模2加法装置将第一多个模2加法装置的每个输出连接到根据生成多项式中的非零系数确定的寄存器级。
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公开(公告)号：US3504356A
公开(公告)日：1970-03-31
申请号：US3504356D
申请日：1967-01-13
Applicant: IBM
Inventor： PATEL ARVIND M , SUMILAS JOHN W
CPC classification number: G11C11/06007 , H03H7/32
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公开(公告)号：US3913068A
公开(公告)日：1975-10-14
申请号：US49319574
申请日：1974-07-30
Applicant: IBM
Inventor： PATEL ARVIND M
CPC classification number: G11B20/1809 , G11B20/1803
Abstract: This specification describes an error correction scheme for digital information serially recorded on a magnetic medium; for example, in stripes oriented diagonally across magnetic tape. The digital information is arranged in segments made up of a set of data sections and two subfield code sections generated on a byte for byte basis from the set of data sections in accordance with Patel U.S. Pat. No. 3,745,528. Thus the first byte of each of the subfield code sections is generated from the first bytes in all the data sections, the second byte of each subfield code section is generated from the second bytes in all the data sections and so on. Each of the sections in the segment is terminated with a synchronization burst. With this arrangement up to two full sections of any data segment can be corrected using these subfield code sections.
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公开(公告)号：US3876978A
公开(公告)日：1975-04-08
申请号：US36693673
申请日：1973-06-04
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HSIAO MU-YUE , PATEL ARVIND M
CPC classification number: G06F11/1076 , G06F11/1008
Abstract: This specification describes a system for preventing the catastrophic loss of data in one storage unit of a storage system comprised of a plurality of such storage units. In this system one of the plurality of storage units is used to store parity bits for the storage system, bit position by bit position. To be more specific, if the data in each of the storage units is considered to be a linear string of bits the storage unit containing the parity bits would contain a parity or Exclusive OR sum of all the first bits of all the storage units or, in a more general case, the j.sup.th bit of the check storage unit is the parity or Exclusive OR sum of all the j bits of all the storage units.
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公开(公告)号：US3868632A
公开(公告)日：1975-02-25
申请号：US39013673
申请日：1973-08-20
Applicant: IBM
Inventor： HONG SE J , PATEL ARVIND M
CPC classification number: G11B20/1833
Abstract: Error correcting apparatus is provided for correcting plural channels in error in a parallel channel information system. The information is encoded in a cross-channel direction as well as along the channel length. The encoded message after storage or transmission is decoded in the cross-channel direction and error correction provided in the in-channel direction in a given number of indicated channels. Orthogonally symmetrical redundancy enhances error correction while tending to minimize hardware. Plural independent codes interact to correct the plural channels in error. The error correcting capabilities of the codes may be matched, no limitation thereto intended.
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Patent Agency Ranking
公开(公告)号：CA1159958A
公开(公告)日：1984-01-03
申请号：CA385488
申请日：1981-09-09
Applicant: IBM
Inventor： PATEL ARVIND M
Abstract: A980035 An improved ECC method and system are disclosed for corrrecting either a random single-bit error, or alternately, a multi-bit error in one byte of a data word from a single syndrome byte. The improvement involves determining the location of the multi-bit error in successive data words which result because of a failure in one of a plurality of failure independent storage units employed for storing a block of multibyte words. The location of the defective byte position is determined by summing each non-zero syndrome byte that is developed for each multi-byte word that is processed to produce a summed syndrome byte .SIGMA.S?0. This summed syndrome byte is then employed to generate a set of vectors which are positionally related in an m-sequence to the summed syndrome byte. A block syndrome byte, developed during the processing of a number of words and representing the sum modulo-2 of the error pattern in each word of the block, is compared to each of the set of vectors. The position of the vector relative to the summed syndrome byte compared to the block syndrome bytes then provides an indication of the byte position in each word which is in error. With the defective byte position identified, the individual syndrome bytes for each word are then employed to develop for each word the correct error pattern for the defective byte position of each word.
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公开(公告)号：CA1014665A
公开(公告)日：1977-07-26
申请号：CA198452
申请日：1974-04-24
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HONG SE J , HSIAO MU-YUE , PATEL ARVIND M
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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公开(公告)号：CA1204874A
公开(公告)日：1986-05-20
申请号：CA446265
申请日：1984-01-27
Applicant: IBM
Inventor： PATEL ARVIND M
Abstract: MULTIBYTE ERROR CORRECTING SYSTEM INVOLVING A TWO-LEVEL CODE STRUCTURE A two-level multibyte error correcting system is disclosed for correcting up to t1 one-byte errors in a codeword in response to processing 2t1 non-zero syndrome bytes at the first level and up to t2 one-byte errors in a codeword in response to processing 2t2 non-zero syndromes bytes at the second level when processing said 2t1 syndrome bytes at said first level does not produce an all zero pattern for said 2t2 syndrome bytes. A relatively long block of data may be divided into subblocks, each of which may contain up to t1 - x onebyte errors that are correctable at the first level by processing 2t1 non-zero syndrome bytes where one identifiable subblock of the word may contain up to t1 + x one-byte errors which are correctable by processing said 2t2 non-zero syndrome bytes where 0 ? x
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公开(公告)号：CA1199410A
公开(公告)日：1986-01-14
申请号：CA438414
申请日：1983-10-05
Applicant: IBM
Inventor： PATEL ARVIND M
IPC: G06F11/10 , G06F20060101 , G06F11/08 , G06K20060101 , G11B5/09 , H03M13/00 , H03M13/15
Abstract: ON-THE-FLY MULTIBYTE ERROR CORRECTING SYSTEM An apparatus and method are disclosed for processing sydrome bytes in a multibyte error correcting system in which up to t errors are correctable by processing 2t syndrome bytes. The method involves converting syndrome bytes into t+l coefficients of the error locator polynomial by predetermined product operations and exclusive-OR operations involving selected syndrome bytes to produce cofactors that correspond to the desired coefficients when less than t errors occurred in the codeword. The cofactors are combined to produce coefficients when t errors occur and the correct set of coefficients are selected in accordance with the number of errors that are detected. The apparatus involves logical circuitry for obtaining sets of coefficients from selected syndrome bytes where each set is associated with a different number of errors in the codeword and in which a set of coefficients associated with t-1 errors is a cofactor of the set of coefficients associated with t errors.
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公开(公告)号：CA1103360A
公开(公告)日：1981-06-16
申请号：CA311729
申请日：1978-09-21
Applicant: IBM
Inventor： PATEL ARVIND M
Abstract: PLURAL CHANNEL ERROR CORRECTING METHODS AND MEANS USING ADAPTIVE REALLOCATION OF REDUNDANT CHANNELS AMONG GROUPS OF CHANNELS Where data is recorded on logically independent sets of parallel channels or tracks, the correction of error of very long (infinite) length cannot be advantageously treated by conventional coding methods unlike finite length error such as single shot or burst noise. To ensure the correction of channels in error from data recovered from a multi-channel storage medium, a fixed number of channels per set are dedicated to error checking bits. In this invention, more than the usual number of channels in error in any one set are made correctable by adaptively reallocating the unused redundant channels in the other set. This is accomplished by encoding and recording in the first redundant channel in. each set vertical parity checks limited to that set while encoding and recording in the second redundant channel of each set, the parity of data taken over both sets of channels in a predetermined positively or negatively sloped direction. With this type of parity information so recorded, then the data obtained from up to three known erroneous channels in any one set may be corrected, provided that two sets together aggregate not more than four channels in error. Advantageously, the vertical and cross-parity checking information can also be used to generate an internal channel-in-error pointer for the first erroneous track in each set. Additionally, this data can be made to yield a second internal channel-in-error pointer in at least one of the sets. Lastly, error patterns are identified upon decoding at the intersection of at least two error syndromes one of which is derived from cross-parity checking bits.
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