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公开(公告)号：CA987031A
公开(公告)日：1976-04-06
申请号：CA159256
申请日：1972-12-18
Applicant: IBM
Inventor： PATEL ARVIND M
Abstract: 1369725 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 6 Oct 1972 [27 Dec 1971] 46153/72 Heading G4A Check bytes C 1 , C 2 are generated from a block of kf-bit bytes Z 1 -Z k arranged in separate tracks or channels (where f = bxm, b and m are integers b ) according to the equations C 1 = Z 1 (+)Z 2 (+)... (+)Z k and C 2 = T # Z 1 ( + )T 2#^ AZ 2 ( +)...(+ )T k#. Z k where T is the companion matrix of a binary primitive polynomial g(x) of degree f, and # is any integer = t(2 f- 1)/(2 b - 1) where t is prime to (2 b -1), and after recording and read-out or after transmission the bytes Z 1 1 -Z k 1 , C 1 1 , C 2 1 are supplied to shift-registers SR1, SR2 to generate syndromes S1 = C 1 1 (+)Z 1 1 (+)Z 2 1 (+)...(+)Z k 1 and S 2 =C 2 1 (+)T # Z 1 1 (+)T 2# Z 2 1 (+)...(+)T k# Z k 1 , any tracks or channels in error are identified and errors in any two tracks or channels are located and corrected. Track pointers P 1 -P k-2 and I 1 -I k are produced, e.g. as in Specification 1,274,630, P i and P j indicating two particular tracks or channels in error and I i indicating the first track or channel in error. For each value of (i-j) there exist fixed values of parameters x, y which depend on the T # chosen. A generator 46 produces the parameters x, y as b-bit binary numbers by gating together the pointers P 1 -P k+2 . The message bytes are entered into SR1 and SR2 in reverse order, Z k 1 first, from distributer 44 with a shift between each byte. After entry of Z 1 1 , the registers are shifted once more as C 1 1 is shifted into SR1 and C 2 1 is shifted into SR2 so that they then hold the syndromes S1, S2 respectively. The number of shifts is counted by a counter B1 preset to (k + 1). A further y shifts are then performed, at the end of which S1 is entered into SR2 whch then holds S 1 (+ )T y# S 2 . A counter B3 gates out SR1 and SR2 after a further x shifts so that S1 and an error pattern e j =T x# (S1( + )T y# S 2 ) are passed to error corrector 68 which generates corrected bytes Z 1 -Z k . A further gating circuit 80 is supplied with S1, e j and signals N 0 , N 1 , N 3 indicating no error, only one track in error, and more than two tracks in error respectively to detect a large percentage of uncorrectable errors. The check bytes C1, C2 are generated by a pair of shift registers SR1, SR2 similar to those shown in Fig. 3.
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