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公开(公告)号：US3693152A
公开(公告)日：1972-09-19
申请号：US3693152D
申请日：1970-12-21
Applicant: IBM
Inventor： HONG SE J
CPC classification number: G06F11/085
Abstract: A decoder error detection circuit having a first and second OR circuit. The first OR circuit having as inputs thereto the half of the outputs from the decoder which represent binary numbers having the same parity. The inputs to the second OR circuit are obtained from the other half of the decoder outputs which represent binary numbers of the opposite parity of those in the first half. The output of the first and second OR circuits is connected to a logic circuit consisting of a NOR circuit and an AND circuit connected to each of said first and second OR circuits in parallel. The outputs of the NOR and AND circuits are OR''ed together to provide an error indication for any single hardware failure in the decoder being checked.
Abstract translation: 一种具有第一和第二OR电路的解码器错误检测电路。 第一OR电路具有来自解码器的表示具有相同奇偶性的二进制数的输出的一半的输入。 从另一半的解码器输出中获得到第二OR电路的输入，它们表示上半部分相反奇偶校验的二进制数。 第一和第二OR电路的输出端连接到由NOR电路和AND电路组成的逻辑电路并联连接到所述第一和第二OR电路中的每一个。 NOR和AND电路的输出被OR组合在一起，为所检查的解码器中的任何一个硬件故障提供错误指示。
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2.发明授权Data coding circuits for encoded waveform with constrained charge accumulation 失效具有受限电荷累积的编码波形的数据编码电路
公开(公告)号：US3906485A
公开(公告)日：1975-09-16
申请号：US36967573
申请日：1973-06-13
Applicant: IBM
Inventor： HONG SE J , OSTAPKO DANIEL L
CPC classification number: H04L25/4906 , G11B20/1426
Abstract: The encoding circuits of this invention provide signals for representing binary data in a storage medium or in a transmission system as a waveform that has a small constrained value of accumulated difference between its positive and negative portions. The waveform has minimum and maximum run lengths between transitions between positive and negative values so that it provides both high density and good clocking. Several new codes are described which can be implemented with fewer logic and storage components than prior codes of this general type.
Abstract translation: 本发明的编码电路提供用于在存储介质或传输系统中表示二进制数据的信号，作为其正负部分之间具有小的累积差的约束值的波形。 波形在正值和负值之间的转换之间具有最小和最大运行长度，从而提供高密度和良好的时钟。 描述了可以使用比该通用类型的先前代码更少的逻辑和存储组件来实现的几个新代码。
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公开(公告)号：US3868632A
公开(公告)日：1975-02-25
申请号：US39013673
申请日：1973-08-20
Applicant: IBM
Inventor： HONG SE J , PATEL ARVIND M
CPC classification number: G11B20/1833
Abstract: Error correcting apparatus is provided for correcting plural channels in error in a parallel channel information system. The information is encoded in a cross-channel direction as well as along the channel length. The encoded message after storage or transmission is decoded in the cross-channel direction and error correction provided in the in-channel direction in a given number of indicated channels. Orthogonally symmetrical redundancy enhances error correction while tending to minimize hardware. Plural independent codes interact to correct the plural channels in error. The error correcting capabilities of the codes may be matched, no limitation thereto intended.
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公开(公告)号：FR2331209A1
公开(公告)日：1977-06-03
申请号：FR7629484
申请日：1976-09-22
Applicant: IBM
Inventor： HONG SE J , OSTAPKO DANIEL L
IPC: H03K19/177 , H03M7/00 , H03K13/25 , H03K19/08
Abstract: This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different decoders. Previously two-bit decoders were arranged on opposite sides of the array to generate input variables from two sets of two different input signals each and feed those input variables to four input lines. Here, instead of using two-bit decoders, four one-bit decoders are positioned on each side. The outputs of these one-bit decoders are programmable to change the connections between them and the input lines of the array. The arrangement permits the decoders to perform one-bit, two-bit decoding on signals on the same side of the input lines, to do two-bit decoding on signals on opposite sides of the array and in combination with other sets of decoders to do three and four-bit decoding of input signals.
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Patent Agency Ranking
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公开(公告)号：FR2295645A1
公开(公告)日：1976-07-16
申请号：FR7533266
申请日：1975-10-20
Applicant: IBM
Inventor： HONG SE J , OSTAPKO DANIEL L
IPC: G06F11/22 , G01R31/3185 , G06F11/10 , H03K19/177 , H03K19/00
Abstract: 1475255 Selective signalling INTERNATIONAL BUSINESS MACHINES CORP 1 Oct 1975 [18 Dec 1974] 40080/75 Heading G4H A logic array with testing apparatus comprises a plurality of decoders feeding input lines of a logic-performing matrix, the matrix incorporating a check line intersecting the input lines for storing information on the number of operative logic means located along each of the input lines. In Fig. 1, input bits at 14 are decoded in pairs by decoders 12a, 12b ... 12, each decoder selecting one of a respective 4 row lines of an AND array 10. The array 10 has FETs at selected row-column intersections to provide on each column line the AND of a respective combination of the row lines. The column lines feed an OR array 24 which similarly has FETs at selected row-column intersections and feeds latches via its row lines. The AND array has an extra column line 21 specifying a parity bit for each row line according to the number of FETs which should be present in it, and the OR array has an extra row line 19 specifying a parity bit for each column line. To test the AND array, a command decoder 36 is used to enable the decoders 12a, 12b ... 12 in turn, each decoder, when enabled, being supplied with appropriate inputs to select all its outputs in turn. As each row line of the AND array is thus selected, the column outputs are loaded into a shift register 48 and parity-checked by an EXCL-OR tree 50. The OR array is then tested by decoupling the two arrays using a mask output 40 of the command decoder 36, and inserting a 1 into the shift register 48 and shifting it along thus selecting the column lines of the OR array in turn, the row outputs being parity-checked in each case by an EXCL-OR tree 54. Another output 42 of the command decoder 36 (used e.g. for normal operation) enables all the decoders 12a, 12b ... 12 and resets the shift register 48. EXCL-ORing may be done serially. Extra redundancy lines could be provided in the arrays.
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公开(公告)号：CA1166759A
公开(公告)日：1984-05-01
申请号：CA400638
申请日：1982-04-07
Applicant: IBM
Inventor： HONG SE J , NAIR RAVINDRA K , SHAPIRO EUGENE
IPC: G06F15/16 , G06F15/177 , G06F15/80 , G06F17/50 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04 , H01L27/118 , H01L21/70 , H01L27/02
Abstract: YO979-023 A HIGH SPEED MACHINE FOR THE PHYSICAL DESIGN OF VERY LARGE SCALE INTEGRATED CIRUCITS Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array of processors may be utilized to wire a much larger array of cells.
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公开(公告)号：CA954222A
公开(公告)日：1974-09-03
申请号：CA143387
申请日：1972-05-30
Applicant: IBM
Inventor： HONG SE J , PATEL ARVIND M
IPC: H03M13/15
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公开(公告)号：CA1040270A
公开(公告)日：1978-10-10
申请号：CA237270
申请日：1975-10-08
Applicant: IBM
Inventor： HONG SE J , OSTAPKO DANIEL L
IPC: G06F11/22 , G01R31/3185 , G06F11/10 , H03K19/177 , G06F11/00
Abstract: This specification describes arrays for performing logic functions which include circuitry for testing the arrays to see if the arrays will perform the logic functions that they were designed to perform. During testing, a gating signal to each of the decoders is used to couple the interrogatior signals of one of these decoders at a time to the input lines of the array. This allows the interrogation of one input line at a time and the detection of the output signals produced by that interrogation on the output lines of the array. To determine whether the output signals are proper, the array contains one or more additional output lines which contain parity or check bits on the circuit elements arranged along each of the input lines. When an input line is interrogated the output signals including those produced by the parity or check bits are exclusively OR'd to determine if the interrogated input line contains the proper number of circuit elements. This circuitry eliminates the need for storing information as to logic functions performed by any particular array and allows a uniform testing sequence to be used in testing all the arrays.
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