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    SEARCH MEMORY, CONTROLLER FOR MEMORY SEARCH, AND MEMORY SEARCH METHOD
    31.
    发明专利
    SEARCH MEMORY, CONTROLLER FOR MEMORY SEARCH, AND MEMORY SEARCH METHOD 审中-公开

    公开(公告)号：JP2003256265A

    公开(公告)日：2003-09-10

    申请号：JP2002039940

    申请日：2002-02-18

    Applicant: IBM

    Inventor： MORI MASAYA ,  WATANABE SHINPEI ,  SUNANAGA TOSHIO

    IPC: G06F12/00 ,  G11C15/00

    Abstract: PROBLEM TO BE SOLVED: To search a large quantity of search targets (contents) at high speed. SOLUTION: A little circuits (a distributor 12 and a controller 13 for search) are added inside the memory. For a search, the algorithm of a quick search, for example, is utilized, memory cells are repeatedly read, the read results are compared and a compare target is narrowed down on the basis of the compared (sized) result. Valid data can be obtained approximately for the middle bus time and cycle time in the conventional case of repeatedly reading the memory. Since comparison and the generation of the address of the next memory cell can be performed in the latter half of the cycle time, the search can be completed just for the bus time of 'the number of times of repeated read of memory cells' + 'one time'. As a result, a CAM function capable of having not several hundreds to several thousands of entry data like a conventional CAM but the number of entry data dividing the size of a DRAM with the number of banks, namely, several tens of thousands of or more entry data can be achieved. COPYRIGHT: (C)2003,JPO

    Memory cell, storage circuit block, data write method and data read method
    35.
    发明专利
    Memory cell, storage circuit block, data write method and data read method 审中-公开
    存储单元，存储电路块，数据写入方法和数据读取方法

    公开(公告)号：JP2002368196A

    公开(公告)日：2002-12-20

    申请号：JP2001161718

    申请日：2001-05-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

    IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/16

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, a storage circuit block, a data write method and data read method in which production yield is high, cost is low, reliability is high, and the chip area can be reduced by reducing the number of metal wiring layers. SOLUTION: A memory cell 12 is configured so as to include metal lines 16 intersecting with bit liens 14 in a no-contact manner therewith, and a second wiring structure 24 for connecting the lines 16 to switching elements 20. A write circuit 26 for making a current flow through the lines 16 and a ground 28 are connected to the lines 16 via a switch 30 for selecting the circuit 26 and the ground 28.

    Abstract translation: 要解决的问题：为了提供一种存储单元，存储电路块，数据写入方法和数据读取方法，其中生产率高，成本低，可靠性高，并且可以通过减少数量来减少芯片面积 的金属布线层。 解决方案：存储单元12被配置为包括与位留置体14以不接触的方式相交的金属线16，以及用于将线16连接到开关元件20的第二布线结构24.用于制造的写入电路26 通过线16和地线28的电流通过用于选择电路26和地面28的开关30连接到线路16。

    SDRAM AND METHOD FOR ACCESSING SDRAM DATA
    36.
    发明专利
    SDRAM AND METHOD FOR ACCESSING SDRAM DATA 失效

    公开(公告)号：JP2000195262A

    公开(公告)日：2000-07-14

    申请号：JP36984998

    申请日：1998-12-25

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407

    Abstract: PROBLEM TO BE SOLVED: To perform seamless access by specifying a bank to be accessed, specifying an address of the data to be accessed in the bank to be accessed, changing the bank specified with a bank specification means in a prescribed order and changing the address specified with an address specification means in the range of the prescribed number of data. SOLUTION: Respective banks are connected to a bank register 32 through an. address register 42 and a decoder 26, and the data of the address specified by the address register 42 of the bank specified by the bank register 32 are outputted. The addresses of the data to be accessed for every bank are stored in the address register 42, and further an increment counter 44 is connected to the address register 42. The increment counter 44 rewrites the information of the address register 42 to the next address of the accessed data, when the access to the data shown by the address register 42 is executed.

    Magnetic storage device
    37.
    发明专利
    Magnetic storage device 有权
    磁性存储器件

    公开(公告)号：JP2005166170A

    公开(公告)日：2005-06-23

    申请号：JP2003403983

    申请日：2003-12-03

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO

    IPC: G11C11/15 ,  G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/16 ,  G11C7/062 ,  G11C14/0081

    Abstract: PROBLEM TO BE SOLVED: To provide an MRAM having a sense amplifier in which hardly any sense current flows into an MTJ element and hardly any voltage is applied and a potential difference that appears on a bit line pair is amplified at a high speed.
    SOLUTION: A sense amplifier 18 comprises cyclically connected CMOS inverters 20 and 22; a P channel MOS transistor TP1 which shuts off power supply during standby and N channel MOS transistors TN5 and TN6 which are used to initialize the outputs of the sense amplifier during standby. A ground terminal 204 of the inverter 20 is connected to a bit line BLT through a transistor TN3 of a bit switch 4 and a ground terminal 224 of the inverter 22 is connected to a bit line BLC through a transistor TN4 of the bit switch 4.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了提供一种具有读出放大器的MRAM，其中几乎没有任何感测电流流入MTJ元件，并且几乎不施加任何电压，并且出现在位线对上的电位差以高速放大 。 解决方案：读出放大器18包括循环连接的CMOS反相器20和22; 在备用期间切断电源的P沟道MOS晶体管TP1和用于在待机期间初始化读出放大器的输出的N沟道MOS晶体管TN5和TN6。 逆变器20的接地端子204通过位开关4的晶体管TN3连接到位线BLT，并且反相器22的接地端子224通过位开关4的晶体管TN4连接到位线BLC。 版权所有（C）2005，JPO＆NCIPI

    Information processor and information processing method, program, data structure and computer readable recording medium
    39.
    发明专利
    Information processor and information processing method, program, data structure and computer readable recording medium 有权
    信息处理器和信息处理方法，程序，数据结构和计算机可读记录介质

    公开(公告)号：JP2004227434A

    公开(公告)日：2004-08-12

    申请号：JP2003016843

    申请日：2003-01-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MORI MASAYA ,  WATANABE SHINPEI ,  SUNANAGA TOSHIO ,  TAKATSU YOSHIHISA

    IPC: G06F12/00 ,  G06F7/00 ,  G06F9/26 ,  G06F9/34 ,  G06F17/00 ,  G06F17/30 ,  H04L29/12

    CPC classification number: G06F17/30949 ,  H04L29/12839 ,  H04L61/6022

    Abstract: PROBLEM TO BE SOLVED: To much more efficiently achieve data registration in a data table and data retrieval from the data table.
    SOLUTION: Data registration in a data table (3) in which the first item data are registered with the corresponding second item data and data retrieval from the data table is executed by using a first pointer table (1) in which a pointer to a portion of registered data in the data table is registered at a storage position shown by a hash value obtained by applying a first hash function (6) to the first item data of the registered data and a second pointer table (2) in which the pointer is registered at a storage position shown by a hash value obtained by applying a second hash function (22) to the first item data of the registered data.
    COPYRIGHT: (C)2004,JPO&NCIPI

    Abstract translation: 要解决的问题：更有效地实现数据表中的数据注册和数据表中的数据检索。 解决方案：通过使用第一指针表（1）来执行数据表（3）中数据表（3）中的数据表，其中第一项数据与对应的第二项数据进行登记，并从数据表中进行数据检索，其中指针 将数据表中的登记数据的一部分登记在通过将第一散列函数（6）应用于登记数据的第一项目数据而获得的哈希值所示的存储位置，以及第二指针表（2） 指针被登记在通过将第二散列函数（22）应用于登记数据的第一项目数据而获得的哈希值所示的存储位置。 版权所有（C）2004，JPO＆NCIPI

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