公开(公告)号：JP2003143198A

公开(公告)日：2003-05-16

申请号：JP2001325695

申请日：2001-10-23

Applicant: IBM

Inventor： MORI MASAYA ,  WATANABE SHINPEI

IPC: H04L12/701 ,  H04L12/741 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide an efficient routing method for shortening a time required for routing. SOLUTION: In a branch B pointer, '11' is stored in a control area, '00010' is in a size storage area and a 'memory address A' is in an information storage area. The existence of a succeeding routing table is indicated by '11' of the control area. It is indicated that the number of branch pointers is 2 =4 in the routing table in a second stage being the succeeding one by '00010' of the size storage area. It is indicated that the number of bits to be referred to is two in a received network address by '00010' of the size storage area. The second and third bits from the highest-order of the network address are referred to in the second-stage of routing table.

公开(公告)号：JP2002298574A

公开(公告)日：2002-10-11

申请号：JP2001095399

申请日：2001-03-29

Applicant: IBM

Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

IPC: G11C11/403 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM and a refreshing method performing successively normal access and refreshing in one operation cycle of a SRAM. SOLUTION: A DRAM 10 comprises an execution instruction means instructing execution of refreshing, an address specifying means specifying a row address of a memory cell to be refreshed, and an execution means refreshing a memory cell of a row address specified by the address specifying means when execution of refreshing is instructed from the execution instruction means.

公开(公告)号：JP2004288226A

公开(公告)日：2004-10-14

申请号：JP2001097911

申请日：2001-03-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

IPC: G11C11/403 ,  G11C11/406

CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/40618

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM which reduces the loss time in accessing at the time of refreshing and performs refreshing for other banks in parallel with the regular accesses and can be used like an SRAM.
SOLUTION: This DRAM comprises a refresh directing means for directing execution of refreshing, a bank specifying means for specifying a bank address of the memory cells to be refreshed, an addressing means for addressing a row address of the memory cells to be refreshed in the specified bank and an execution means for refreshing the memory cells of the row address addressed by the addressing means in the bank specified by the bank specifying means in response to the direction of execution of refresh from the refresh directing means.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004015592A

公开(公告)日：2004-01-15

申请号：JP2002168178

申请日：2002-06-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MORI MASAYA ,  WATANABE SHINPEI ,  SUNANAGA TOSHIO

IPC: H04L12/70 ,  H04L12/741 ,  H04L12/771 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To fast retrieve an optional MAC (media access control) address among a large number of MAC addresses in a large-scale switch, or the like used in a network. SOLUTION: The structure of a MAC pointer table 10 is provided which has the number of entries of N bits (e.g. 14 bits) selected from among bits constituting an MAC address 18, wherein each of the entries 14 includes a pointer for designating an entry table 12 of the MAC address 18, and the pointer is composed of N bits (e.g., 14 bits) of the MAC address 18. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003256265A

公开(公告)日：2003-09-10

申请号：JP2002039940

申请日：2002-02-18

Applicant: IBM

Inventor： MORI MASAYA ,  WATANABE SHINPEI ,  SUNANAGA TOSHIO

IPC: G06F12/00 ,  G11C15/00

Abstract: PROBLEM TO BE SOLVED: To search a large quantity of search targets (contents) at high speed. SOLUTION: A little circuits (a distributor 12 and a controller 13 for search) are added inside the memory. For a search, the algorithm of a quick search, for example, is utilized, memory cells are repeatedly read, the read results are compared and a compare target is narrowed down on the basis of the compared (sized) result. Valid data can be obtained approximately for the middle bus time and cycle time in the conventional case of repeatedly reading the memory. Since comparison and the generation of the address of the next memory cell can be performed in the latter half of the cycle time, the search can be completed just for the bus time of 'the number of times of repeated read of memory cells' + 'one time'. As a result, a CAM function capable of having not several hundreds to several thousands of entry data like a conventional CAM but the number of entry data dividing the size of a DRAM with the number of banks, namely, several tens of thousands of or more entry data can be achieved. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000195262A

公开(公告)日：2000-07-14

申请号：JP36984998

申请日：1998-12-25

Applicant: IBM

Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To perform seamless access by specifying a bank to be accessed, specifying an address of the data to be accessed in the bank to be accessed, changing the bank specified with a bank specification means in a prescribed order and changing the address specified with an address specification means in the range of the prescribed number of data. SOLUTION: Respective banks are connected to a bank register 32 through an. address register 42 and a decoder 26, and the data of the address specified by the address register 42 of the bank specified by the bank register 32 are outputted. The addresses of the data to be accessed for every bank are stored in the address register 42, and further an increment counter 44 is connected to the address register 42. The increment counter 44 rewrites the information of the address register 42 to the next address of the accessed data, when the access to the data shown by the address register 42 is executed.

公开(公告)号：JPS61138292A

公开(公告)日：1986-06-25

申请号：JP25774484

申请日：1984-12-07

Applicant: Ibm

Inventor： SHIBATA ICHIRO ,  WATANABE SHINPEI

IPC: G09G5/10 ,  G09G1/16 ,  G09G5/02 ,  G09G5/06 ,  G09G5/30

CPC classification number: G09G5/06

公开(公告)号：JPS60252394A

公开(公告)日：1985-12-13

申请号：JP10188684

申请日：1984-05-22

Applicant: IBM

Inventor： AOKI YUTAKA ,  WATANABE SHINPEI

IPC: G09G5/00 ,  G06F3/147 ,  G06F3/153 ,  G06T11/00 ,  G09G5/02 ,  G09G5/39

公开(公告)号：JP2004288225A

公开(公告)日：2004-10-14

申请号：JP2001095368

申请日：2001-03-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI ,  HOSOKAWA KOJI

IPC: G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4097

CPC classification number: G11C7/1066 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM and an access method to the DRAM with which a high data rate can be obtained in a Random Row Access.
SOLUTION: The DRAM and the access method of the DRAM is constituted so that eight subword lines 16 are chosen from 512 subword lines 16 by selecting one main word line from a plurality of main word lines 14 and one subword line 16 is selected by a signal and an enable signal for selecting the subword line 16.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004079093A

公开(公告)日：2004-03-11

申请号：JP2002239321

申请日：2002-08-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI ,  MORI MASAYA

IPC: H03K5/00 ,  G11C11/406 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To provide a timing circuit of which the power consumption is low and the clock period can be varied.
SOLUTION: This timing circuit comprises a clock generator 11, comparators 12, 13 comparing inputted control voltage TDV with reference voltage VR, holding circuits 18, 19 holding an output of the comparator, and circuits 20, 21, 22 generating a timing pulse TDT outputted from an output of the holding circuit and a clock outputted by a clock generator. The comparator receives a first clock SS outputted by the clock generator, and is operated only for a time corresponding to a short pulse width of the first clock SS.
COPYRIGHT: (C)2004,JPO