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公开(公告)号：DE2705680A1
公开(公告)日：1977-09-01
申请号：DE2705680
申请日：1977-02-11
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: Disclosed is a decoder which receives a number of coded binary-weighted input signals and which provides, on a plurality of output signal lines, a threshold related to the coded value of the input signals. The threshold is defined at the output as a consecutive sequence of output signal lines having a binary 0 value on one side of the threshold, and a consecutive sequence of output signals on the other side of the threshold having a binary value of 1. In one embodiment, a single level of binary logic receives n input signals and produces a threshold on m = 2n-1 output signal lines. A second embodiment receives n input signals which are divided into groups of signals, each group of which is applied to an intermediate threshold generator, the outputs of which are combined in a final level to provide m output signals. A further embodiment of the threshold decoder receives two groups of input signals which are combined in a first level of intermediate threshold generators, the outputs of which are then combined in a final stage which may produce more than one threshold on the output signal lines. Another further embodiment of the threshold decoder discloses a plurality of groups of input signal lines, combined in a plurality of intermediate threshold generators, the outputs of which are combined in a final level of logic to produce, selectively, a like plurality of thresholds on the output signal lines.
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公开(公告)号：FR2296968A1
公开(公告)日：1976-07-30
申请号：FR7534723
申请日：1975-11-05
Applicant: IBM
Inventor： WEINBERGER ARNOLD
IPC: G11C17/00 , H03K17/00 , H03K19/177 , H03K19/20
Abstract: This specification describes a programmable logic array (PLA) in which the readout table or OR array for the PLA is broken into two segments and the segments placed on opposite sides of the search table or AND array for the PLA. The output lines for the AND array can then be split so that outputs on one segment of those lines are fed to the OR array on one side and outputs on the other portion of those lines are fed to the OR array on the opposite side. Likewise the output lines in the OR arrays can be broken so that different functions can be fed out to opposite sides of the OR arrays. It is also possible to break input lines in both the OR and AND arrays to isolate functions from one another.
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公开(公告)号：GB1270909A
公开(公告)日：1972-04-19
申请号：GB232071
申请日：1971-01-18
Applicant: IBM
Inventor： SCHMOOKLER MARTIN STANLEY , WEINBERGER ARNOLD
Abstract: 1,270,909. Binary coded decimal addition. INTERNATIONAL BUSINESS MACHINES CORP. 18 Jan., 1971 [13 Feb., 1970], No. 2320/71. Heading G4A. A BCD adder for adding n digit operands has logic circuitry for adding each pair of decimal digits which receives C in , the carry in to that pair, and generates Cd, the carry cut to that pair. The parallel logic circuitry can generate Pi (the OR function of the i bit of each digit where i=1, 2, 4, or 8) and Gi (the AND function of the i bit). It can be proved that C 1 =G 1 + P 1 C in , K=G 8 +P 5 P 4 +P 8 P 2 +G 4 P 2 , and L= P 8 +G 4 +P 4 G 2 , and hence that the carry out Cd = K + LC 1 . Using these formula it is possible to generate the carry for each pair of decimal digits without generating the binary carries of each bit. Theory.-When two BCD digits A, B are added a carry should be produced when the sum is ten or more or when the sum is 9 and there is a carry from the previous stage. Where A, B is logical AND of A and B and A+B is logical OR for A and B, the carry Cd=A 8 B 5 +A 5 B 4 + A 8 B 2 +B 8 A 2 +A 8 A 1 B 1 &c. (i.e. all possible combinations equalling 10 or more) [A 8 A 1 +A 8 B 1 + B 8 B 1 &c....]Cd-1 (i.e. all possible combinations equalling 9 plus I for a carry). The above formula can be derived from this. The circuitry.-Figs. 1 to 3 (not shown), show a 2 digit, four logic level, adder in which the decimal sums of the higher and lower order digits are added separately. Figs. 4-6 (not shown), are similar but use three logic levels and Figs. 7 to 12 (not shown) show a six digit, eight logic level adder using carry look ahead.
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公开(公告)号：DE1616438A1
公开(公告)日：1971-04-08
申请号：DEJ0035964
申请日：1968-03-19
Applicant: IBM
Inventor： WEINBERGER ARNOLD
IPC: H01L27/02 , H01L27/088 , H01L27/112 , H01L27/118 , H03K19/0944 , H05K
Abstract: 1,193,025. Transistor logic circuits. INTERNATIONAL BUSINESS MACHINES CORP. 8 March, 1968 [23 March, 1967], No. 11299/68. Heading H3T. [Also in Divisions G4 and H1] A NOR logic element used in the integrated adder accumulator described in the Division G4 abridgment is shown in Fig. 1A. It consists of N parallel connected NPN input IGFETS 1 to N in series with an NPN load IGFET 5. When gates G are off no current flows in the input transistors and the output voltage at 7 is therefore V s , but when one or more gates are on the output voltage falls to zero.
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Patent Agency Ranking
公开(公告)号：CH627580A5
公开(公告)日：1982-01-15
申请号：CH1573476
申请日：1976-12-14
Applicant: IBM
Inventor： BRYANT LOUIS RONALD , PEDERSEN RAYMOND JAMES , WEINBERGER ARNOLD
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公开(公告)号：CA1099411A
公开(公告)日：1981-04-14
申请号：CA272263
申请日：1977-02-21
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: THRESHOLD DECODER Disclosed is a decoder which receives a number of coded binary-weighted input signals and which provides, on a plurality of output signal lines, a threshold related to the coded value of the input signals. The threshold is defined at the output as a consecutive sequence of output signal lines having a binary 0 value on one side of the threshold, and a consecutive sequence of output signals on the other side of the threshold having a binary value of 1. In one embodiment, a single level of binary logic receives n input signals and produces a threshold onm = 2n-1 output signal lines. A second embodiment receives n input signals which are divided into groups of signals, each group of which is applied to an intermediate threshold generator, the outputs of which are combined in a final level to provide m output signals. A further embodiment of the threshold decoder receives two groups of input signals which are combined in a first level of intermediate threshold generators, the outputs of which are then combined in a final stage which may produce more than one threshold on the output signal lines. Another further embodiment of the threshold decoder discloses a plurality of groups of input signal lines, combined in a plurality of intermediate threshold generators, the outputs of which are combined in a final level of logic to produce, selectively, a like plurality of thresholds on the output signal lines. D-PO9-75-009
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公开(公告)号：CA1060959A
公开(公告)日：1979-08-21
申请号：CA237279
申请日：1975-10-08
Applicant: IBM
Inventor： WEINBERGER ARNOLD
IPC: G11C17/00 , H03K17/00 , H03K19/177 , H03K19/20
Abstract: CLUSTERED LOGIC ARRAYS This specification describes a programmable logic array (PLA) in which the readout table or OR array for the PLA is broken into two segments and the segments placed on opposite sides of the search table or AND array for the PLA. The output lines for the AND array can then be split so that outputs on one segment of those lines are fed to the OR array on one side and outputs on the other portion of those lines are fed to the OR array on the opposite side. Likewise the output lines in the OR arrays can be broken so that different functions can be fed out to opposite sides of the OR arrays. It is also possible to break input lines in both the OR and AND arrays to isolate functions from one another.
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公开(公告)号：CA1059637A
公开(公告)日：1979-07-31
申请号：CA262158
申请日：1976-09-27
Applicant: IBM
Inventor： ARPS RONALD B , BAHL LALIT R , WEINBERGER ARNOLD
Abstract: An apparatus is disclosed for compressing a p x q image array of two-valued (black/white) sample points. The image array points are serially applied to the apparatus in consecutive raster scan lines. In response, the apparatus simultaneously forms two matrices respectively representing a high order p x q predictive error array and a p x q array of location events (such as the raster leading edges of all objects in the image). Improved compression is achieved by selecting between the more compression efficient of two methods for encoding the position of errors in the prediction error array. This alternative methods are conventional run-length coding and a novel form of reference encoding, used selectively but to significant advantage. Thus, a run-length compression codeword is formed from the count C of non-errors between consecutive errors (in response to the occurrence of each error in the jth bit position of the ith scan line of the predictive error array) upon either C?T, where T is a threshold, or C>T and there being no occurrence of a line difference encoding for the error (where i, j, C and T have positive integers). A line difference codeword with difference value v is generated upon the joint event of C>T and either the single or multiple occurrence of location events in the ith-1 scan line of the location event array within the bit position range of B?r?(j+n), where positive integer B is the greater of function D(T,v) and (j-n), and the number of intervening location events, s, within the bit positioned range of D(T,v)?q
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