公开(公告)号：JP2005339562A

公开(公告)日：2005-12-08

申请号：JP2005156011

申请日：2005-05-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BUSABA FADI Y ,  POWELL LAWRENCE JOSEPH ,  SCHMOOKLER MARTIN STANLEY ,  VADEN MICHAEL THOMAS ,  WEBBER DAVID ALLAN

IPC: G06F7/38 ,  G06F11/00 ,  G06F11/22 ,  G06F11/267

CPC classification number: G06F11/2226

Abstract: PROBLEM TO BE SOLVED: To provide a method for finding a fault in a circuit. SOLUTION: This method comprises creation of a first result of a function selected by executing the function selected for a certain operand, and the selected function employs a mask. When the function is executed, an anti-mask of the mask is created, and the modulo of the anti-mask is calculated. The modulo function of the first result of the selected function is calculated and a third result is obtained. Next, the modulo of the operand is calculated to obtain a fourth result, and then a second function is executed for the second result and the third result to obtain a fifth result. In response to comparison of the fifth result with the fourth result, a signal indicating a fault in a circuit is transmitted. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在电路中发现故障的方法。 解决方案：该方法包括通过执行为特定操作数选择的功能而选择的功能的第一结果的创建，并且所选择的功能采用掩码。 当执行该功能时，产生掩模的反掩模，并计算防掩模的模数。 计算所选函数的第一个结果的模函数，并获得第三个结果。 接下来，计算操作数的模数以获得第四结果，然后对第二结果执行第二函数，并且执行第三结果以获得第五结果。 响应于第五结果与第四结果的比较，发送指示电路中的故障的信号。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH11288411A

公开(公告)日：1999-10-19

申请号：JP892699

申请日：1999-01-18

Applicant: IBM

Inventor： SCHMOOKLER MARTIN STANLEY ,  SENZIG DONALD NORMAN

IPC: G06F7/544 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F17/17

Abstract: PROBLEM TO BE SOLVED: To reduce the number of times of repetition by accurately estimating a square root, an inverse square root and a reciprocal by calculating an estimated reciprocal through subtracting the product of a normalized input value and a first constant from a second constant. SOLUTION: A full accuracy input (x) is divided into a high-order part xH and a low-order part xL, then the high-order part xH is sent to a look-up table(LUT) 200. The LUT 200 sends a first constant as an inclination to a booth multiplexer 202 and sends a second constant as an offset to a multiplier array/ adder 204. Then, the multiplier array/adder 204 calculates an estimated reciprocal by adding the product of one part of the normalized input value and the first constant to the second constant, or by subtracting that product from the second constant. Thus, a square root, an inverse square root and a reciprocal can be accurately estimated and the number of times of repetition can be reduced.

公开(公告)号：DE3773582D1

公开(公告)日：1991-11-14

申请号：DE3773582

申请日：1987-07-21

Applicant: IBM

Inventor： MASLEID ROBERT PAUL ,  SCHMOOKLER MARTIN STANLEY

IPC: H03K19/017 ,  H03K19/177

Abstract: A programmable logic array comprises: a plurality of electrically isolated input lines (eg 204, 206, 208, 210); input means (200) for addressing the plurality of input lines and directing an input signal to an addressed one thereof; a plurality of electrically isolated output lines (220, 228) positioned to form a plurality of nonconductive intersections with said input lines; an individual transistor (212, 214, 216, 218, 230, 232, 234, 236) disposed at each intersection, the control electrode of the transistor being connected to one of the input lines and one current flow electrode of the transistor being connected to one of the output lines and the other current flow electrode of the transistor being connected to a selected one of two potential sources (GND, +V), the selection being made in the course of programming the array, whereby a programmed output signal is obtained on the output line to which said one currant flow electrode is connected when an input signal is directed to an addressed input line.

公开(公告)号：BR8706008A

公开(公告)日：1988-06-28

申请号：BR8706008

申请日：1987-11-09

Applicant: IBM

Inventor： RUNYON STEPHEN LARRY ,  SCHMOOKLER MARTIN STANLEY

IPC: H03K3/3565 ,  H03K17/693 ,  H04J3/00

公开(公告)号：GB1270909A

公开(公告)日：1972-04-19

申请号：GB232071

申请日：1971-01-18

Applicant: IBM

Inventor： SCHMOOKLER MARTIN STANLEY ,  WEINBERGER ARNOLD

IPC: G06F7/494 ,  G06F7/50

Abstract: 1,270,909. Binary coded decimal addition. INTERNATIONAL BUSINESS MACHINES CORP. 18 Jan., 1971 [13 Feb., 1970], No. 2320/71. Heading G4A. A BCD adder for adding n digit operands has logic circuitry for adding each pair of decimal digits which receives C in , the carry in to that pair, and generates Cd, the carry cut to that pair. The parallel logic circuitry can generate Pi (the OR function of the i bit of each digit where i=1, 2, 4, or 8) and Gi (the AND function of the i bit). It can be proved that C 1 =G 1 + P 1 C in , K=G 8 +P 5 P 4 +P 8 P 2 +G 4 P 2 , and L= P 8 +G 4 +P 4 G 2 , and hence that the carry out Cd = K + LC 1 . Using these formula it is possible to generate the carry for each pair of decimal digits without generating the binary carries of each bit. Theory.-When two BCD digits A, B are added a carry should be produced when the sum is ten or more or when the sum is 9 and there is a carry from the previous stage. Where A, B is logical AND of A and B and A+B is logical OR for A and B, the carry Cd=A 8 B 5 +A 5 B 4 + A 8 B 2 +B 8 A 2 +A 8 A 1 B 1 &c. (i.e. all possible combinations equalling 10 or more) [A 8 A 1 +A 8 B 1 + B 8 B 1 &c....]Cd-1 (i.e. all possible combinations equalling 9 plus I for a carry). The above formula can be derived from this. The circuitry.-Figs. 1 to 3 (not shown), show a 2 digit, four logic level, adder in which the decimal sums of the higher and lower order digits are added separately. Figs. 4-6 (not shown), are similar but use three logic levels and Figs. 7 to 12 (not shown) show a six digit, eight logic level adder using carry look ahead.

公开(公告)号：SG72922A1

公开(公告)日：2000-05-23

申请号：SG1999000309

申请日：1999-02-01

Applicant: IBM

Inventor： SCHMOOKLER MARTIN STANLEY ,  SENZIG DONALD NORMAN

IPC: G06F7/544 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F17/17

Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1 ≤ x

公开(公告)号：BR8703295A

公开(公告)日：1988-04-05

申请号：BR8703295

申请日：1987-06-29

Applicant: IBM

Inventor： MASLEID ROBERTO PAUL ,  SCHMOOKLER MARTIN STANLEY

IPC: H03K19/017 ,  H03K19/177 ,  G11C17/00 ,  H03K17/04

Abstract: A programmable logic array comprises: a plurality of electrically isolated input lines (eg 204, 206, 208, 210); input means (200) for addressing the plurality of input lines and directing an input signal to an addressed one thereof; a plurality of electrically isolated output lines (220, 228) positioned to form a plurality of nonconductive intersections with said input lines; an individual transistor (212, 214, 216, 218, 230, 232, 234, 236) disposed at each intersection, the control electrode of the transistor being connected to one of the input lines and one current flow electrode of the transistor being connected to one of the output lines and the other current flow electrode of the transistor being connected to a selected one of two potential sources (GND, +V), the selection being made in the course of programming the array, whereby a programmed output signal is obtained on the output line to which said one currant flow electrode is connected when an input signal is directed to an addressed input line.