公开(公告)号：DE10330812B4

公开(公告)日：2006-07-06

申请号：DE10330812

申请日：2003-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: G06F13/16 ,  G06F12/00 ,  G11C5/06 ,  G11C7/10 ,  G11C11/41

公开(公告)号：DE10260184B4

公开(公告)日：2005-08-25

申请号：DE10260184

申请日：2002-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS

IPC: G11C29/26 ,  H05K1/02 ,  H05K1/18 ,  G11C29/00

Abstract: The memory module contains electronic circuit board with numerous memory components (1-4) and tester (5) for electric functions of components. Tester is fitted on circuit board separately from components, with specified design. The design responds to supply of clock pulse signal generated outside memory module, to provide control signals, address signal, and data values to be stored, which are transmitted to each memory component over control (11) and address lines (12) with nodal points, from which they branch out to each component.

公开(公告)号：DE10344818A1

公开(公告)日：2005-04-28

申请号：DE10344818

申请日：2003-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076

Abstract: A calibration device for adjusting the relative phase between two signals (CLK, DTS) which are generated in a controller in synchronism to one another and then sent via separate lines to the storage module. A measurement device (40) measures the relative phase between the two received signals and a feedback loop containing a phase controlled correction device (60) and the measurement device (40) is designed for generating adjustment or setting information (STL). The correction circuit (60) is arranged in the controller (110) and is designed for influencing the relative phase between the two signals to be sent to the storage module (120), and the feedback loop contains a feedback signal connection (RLDL) leading from the storage module (120) to the controller (110). An independent claim is included for an arrangement of several calibration devices.

公开(公告)号：DE10330812A1

公开(公告)日：2005-04-14

申请号：DE10330812

申请日：2003-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10 ,  G11C11/41

公开(公告)号：DE10306062B3

公开(公告)日：2004-08-19

申请号：DE10306062

申请日：2003-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS

IPC: G11C8/18 ,  G11C11/406 ,  G06F12/16 ,  G11C5/04

Abstract: The memory module (1) has a number of integrated semiconductor memory elements (10-18,20-28) arranged on a carrier substrate together with a separate refresh-control circuit (30) coupled to the integrated semiconductor memory elements and receiving external address or command signals (ADR,CMD), for providing a refresh command (AREF) or a refresh command sequence for the memory cells of a selected integrated semiconductor memory element.