公开(公告)号：DE10334779A1

公开(公告)日：2005-03-10

申请号：DE10334779

申请日：2003-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM ,  JAKOBS ANDREAS

IPC: G11C5/06 ,  G11C7/22 ,  G11C11/4076 ,  G11C5/04

Abstract: A semiconductor memory module comprises chips (1-8) with clock (CLK), command and address (C/A) and data signals through an internal buffer chip (10) with bus connections. The chips have separate read and write clock signal inputs led in a loop (S) from the buffer chip to the end of each row (I,II) for reading and writing.

公开(公告)号：DE10307548A1

公开(公告)日：2004-09-09

申请号：DE10307548

申请日：2003-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  BRAUN GEORG

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/42

Abstract: Commands including multiple segments (BS) having multiple elements (E) are generated and transferred to memory modules (16) via a transmission bus (22). The bus transmits the elements of a segment in parallel. The commands include a respective select command segment (R) for selecting one or more memory ranks (20). Each of the memory ranks has a one-to-one correspondence with at least one element of the select command segment. Independent claims are included for a method of communicating in a synchronous memory system; and for a protocol for communication in a synchronous memory system.

公开(公告)号：DE10305837A1

公开(公告)日：2004-09-02

申请号：DE10305837

申请日：2003-02-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS

IPC: G11C11/408

Abstract: The device has a carrier substrate (50) with connections (40) for feeding address and command signals, integrated memory components (10-18;20-28) on the substrate and a separate access control circuit (30) on the substrate with inputs connected to the connections for feeding address and command signals and outputs to the integrated memory components. The access control circuit generates column and row addresses (CADR,RADR) from memory access addresses.

公开(公告)号：DE10239322B4

公开(公告)日：2004-07-08

申请号：DE10239322

申请日：2002-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/02 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/407

公开(公告)号：DE10245546B3

公开(公告)日：2004-05-13

申请号：DE10245546

申请日：2002-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  JANIK THOMAS ,  MENKE MANFRED ,  PLAETTNER ECKEHARD

IPC: G11C11/406 ,  G11C7/24 ,  G11C11/4076

Abstract: A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

公开(公告)号：DE102005042522A1

公开(公告)日：2007-05-03

申请号：DE102005042522

申请日：2005-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLEINIG TORSTEN ,  JAKOBS ANDREAS ,  HINZ TORSTEN ,  MUELLER DAVID

IPC: G11C7/10 ,  G11C11/407

Abstract: The circuit (100) has a memory circuit for storing data with control connection for applying a control signal. A control circuit (130) is provided for controlling controllable switches (170). The control circuit conductively controls the switches, when the control signal exhibits a level before creating the starting data of a data set at the data connection, where the control circuit is controlled by another control signal. The control circuit disables the controllable switch, when the former control signal exhibits the level after creating the last data of a data set at the data connection.

公开(公告)号：DE102005008151A1

公开(公告)日：2006-08-24

申请号：DE102005008151

申请日：2005-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  HINZ TORSTEN ,  ZARYOUH BENAISSA

IPC: H03L7/081

Abstract: Controllable delay elements (6) in series form delay chain (2) and phase detector (3) generates control signal, dependent on periodic input signal, and periodic signal delayed by delay chain.Circuit contains selection unit (7), coupled to each delay element to apply output signal of element to output of DLL circuit. Compensation circuit (9-11) modifies selection signal (AS) so that additional delay between periodic input and output signal of DLL circuit is compensated.

公开(公告)号：DE102004037164A1

公开(公告)日：2006-03-23

申请号：DE102004037164

申请日：2004-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  JAKOBS ANDREAS

IPC: H03L7/081 ,  G11C11/4063

Abstract: A device for the regulated delay of a clock signal is proposed, which comprises a delay means in order to generate a delayed clock signal, and comparison means for the phase comparison of the delayed clock signal with a reference clock signal. The reference clock signal is in this connection preferably formed by the clock signal or is derived therefrom. On the basis of a comparison signal generated by the comparison means, a digital control signal is generated for controlling the delay means. The comparison means are configured so as to generate the comparison signal as a digitally coded signal that has a pulse duty ratio and a frequency that are determined by a further clock signal that is generated independently of the first clock signal, and that preferably has twice the frequency of the first clock signal.

公开(公告)号：DE10330811A1

公开(公告)日：2005-02-17

申请号：DE10330811

申请日：2003-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4063

公开(公告)号：DE10306149A1

公开(公告)日：2004-09-02

申请号：DE10306149

申请日：2003-02-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  JAKOBS ANDREAS

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/12 ,  G11C8/06

Abstract: Method for allocating memory addresses to a buffer component (2) for one or more memory assemblies (3) associated with the buffer. Memory is assigned in an initializing mode and has the following steps: allocating of available memory addresses to the initializing data; assignment of memory address data for one or more memory assemblies; generation of second initializing data and; transmission of the second set of initializing data. An independent claim is made for a buffer component.