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    2.
    发明专利
    未知

    公开(公告)号：DE60230191D1

    公开(公告)日：2009-01-15

    申请号：DE60230191

    申请日：2002-06-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KUZMENKA MAKSIM

    IPC: H01R13/20 ,  H01R12/24 ,  H01R12/61 ,  H01R13/28 ,  H01R13/631 ,  H05K3/32

    Abstract: A circuit part comprises a support (10, 12) and conductor teeth (14) provided on the support, wherein the conductor teeth (14) are designed to be electrically and mechanically connected to respective conductor teeth (14) provided on another support in the manner of a zipper. The teeth are provided with a spring mechanism to improve the electrical contact between adjacent teeth when connected. The spring mechanism comprises a respective gap formed in the teeth, wherein when connected, the teeth are compressed by reducing the gap so that a restoring force is produced.

    5.
    发明专利
    未知

    公开(公告)号：DE60210170D1

    公开(公告)日：2006-05-18

    申请号：DE60210170

    申请日：2002-07-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KUZMENKA MAKSIM ,  KOROTKOV KONSTANTIN

    IPC: G06F13/40

    Abstract: A memory system comprises a memory controller (14), a plurality of memory modules (10, 12) and a memory bus (16) connected to the memory controller (14) and branching into a plurality of sub-busses (20, 22), each of which is connected to a memory module (10, 12). A sub-bus (20, 22) has a diode (24, 26) associated therewith for isolating a memory module (10, 12) connected to that sub-bus (20, 22) from the memory bus (16).

    6.
    发明专利
    未知

    公开(公告)号：DE10332616B3

    公开(公告)日：2005-03-17

    申请号：DE10332616

    申请日：2003-07-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JAKOBS ANDREAS ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

    IPC: G11C5/06 ,  G11C7/22

    Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

    7.
    发明专利
    未知

    公开(公告)号：DE10229119B4

    公开(公告)日：2004-12-09

    申请号：DE10229119

    申请日：2002-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

    IPC: H01R12/16 ,  H01R12/18 ,  H01R12/71 ,  H01R13/66 ,  H01R13/68 ,  H01R24/00

    Abstract: A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching assemblies, which have compatible interfaces. The connector has a plurality of receptacle devices with contact elements and internal contact connections between corresponding contact elements, as a result of which, the length of the connections between the switching assemblies is reduced, signal propagation times are shortened and a higher clock rate for operating the switching assemblies is made possible.

    8.
    发明专利
    未知

    公开(公告)号：DE10250156A1

    公开(公告)日：2004-05-13

    申请号：DE10250156

    申请日：2002-10-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRAUN GEORG ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

    IPC: G11C5/04 ,  G11C5/06 ,  H05K1/14 ,  G11C7/10 ,  G11C7/02

    Abstract: In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.

    10.
    发明专利
    未知

    公开(公告)号：DE60221407D1

    公开(公告)日：2007-09-06

    申请号：DE60221407

    申请日：2002-11-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KUZMENKA MAKSIM

    IPC: G11C5/00 ,  H05K1/14 ,  H05K3/22

    Abstract: A memory system has a circuit board (100) provided with a first slot connector (104) into which a first memory module (114) is inserted. A second slot connector (106) is provided into which a second memory module (116) is inserted. The first and the second memory modules (114, 116) are connected via a flexible bridge (138). The flexible bridge extends from respective ends of the memory modules opposite to that ends thereof which are inserted into the connector slots. The flexible bridge (138) provides a signal bus between the memory modules (114, 116).

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