公开(公告)号：AU4100696A

公开(公告)日：1996-05-23

申请号：AU4100696

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  CALLAHAN SHELAGH ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M

IPC: G06F13/38 ,  G06F13/00 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64 ,  G06F9/02

Abstract: A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

公开(公告)号：AU3973095A

公开(公告)日：1996-05-23

申请号：AU3973095

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.