公开(公告)号：GB2308533B

公开(公告)日：1999-04-07

申请号：GB9707611

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

公开(公告)号：AU688175B2

公开(公告)日：1998-03-05

申请号：AU4100696

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  CALLAHAN SHELAGH ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M

IPC: G06F13/38 ,  G06F13/00 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64 ,  G06F9/02

Abstract: A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

公开(公告)号：BR9509458A

公开(公告)日：1998-01-06

申请号：BR9509458

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAM BALA

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

公开(公告)号：AU703388B2

公开(公告)日：1999-03-25

申请号：AU3973095

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

公开(公告)号：AU4019995A

公开(公告)日：1996-05-23

申请号：AU4019995

申请日：1995-10-30

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  H04L12/40 ,  H04L12/64 ,  G06F13/12

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

公开(公告)号：DE19581234B4

公开(公告)日：2008-03-20

申请号：DE19581234

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/36 ,  G06F13/37 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

公开(公告)号：DE19581234T1

公开(公告)日：1997-10-02

申请号：DE19581234

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64 ,  G06F13/37

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

公开(公告)号：HK1002784A1

公开(公告)日：1998-09-18

申请号：HK98101350

申请日：1998-02-20

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  H04L12/40 ,  H04L12/64 ,  G06F ,  H04L

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

公开(公告)号：HK1002781A1

公开(公告)日：1998-09-18

申请号：HK98101346

申请日：1998-02-20

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  CALLAHAN SHELAGH ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M

IPC: G06F20060101 ,  G06F13/38 ,  G06F13/00 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

公开(公告)号：GB2308533A

公开(公告)日：1997-06-25

申请号：GB9707611

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Logic is provided for a bus controller (14), a number of 1:n bus signal distributors (18), and a number of bus interfaces (22) of a hierarchical bus assembly (26) for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly (26). The hierarchical bus assembly (26) is used to serially interface a number of isochronous and asynchronous peripherals (16c-f) to the system unit (12) of a computer system (10). These serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance with the transaction protocols. In some embodiments, these serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.