公开(公告)号：US11935808B2

公开(公告)日：2024-03-19

申请号：US16831078

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/49568

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US20240063089A1

公开(公告)日：2024-02-22

申请号：US17891738

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Yoshihiro Tomita ,  Omkar Karhade ,  Haris Khan Niazi ,  Tushar Talukdar ,  Mohammad Enamul Kabir ,  Xavier Brun ,  Feras Eid

IPC: H01L23/46

CPC classification number: H01L23/46 ,  G02B6/4268

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.

公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20230420436A1

公开(公告)日：2023-12-28

申请号：US17846109

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L23/5226 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/08145

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.

公开(公告)号：US11804441B2

公开(公告)日：2023-10-31

申请号：US16902910

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73253

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate including a first metal layer and a second metal layer; a cavity in the substrate, wherein a portion of the first metal layer in the substrate and a portion of the second metal layer in the substrate are exposed in the cavity; and a bridge component in the cavity, the bridge component includes a first conductive contact at a first face and a second conductive contacts at an opposing second face, wherein the second face of the bridge component is between the first face of the bridge component and a bottom surface of the cavity in the substrate, and wherein the second conductive contact is electrically coupled to the portion of the first metal layer in the cavity.

公开(公告)号：US20230343769A1

公开(公告)日：2023-10-26

申请号：US17728147

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Steve Cho ,  Babak Sabi

IPC: H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L21/78 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155

Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.

公开(公告)号：US11798865B2

公开(公告)日：2023-10-24

申请号：US16291314

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Ravindranath Mahajan ,  Debendra Mallik ,  Sujit Sharan ,  Digvijay Raorane

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US11742261B2

公开(公告)日：2023-08-29

申请号：US18089535

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Ravindranath Mahajan ,  Debendra Mallik ,  Sujit Sharan ,  Digvijay Raorane

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US11694959B2

公开(公告)日：2023-07-04

申请号：US16524748

申请日：2019-07-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Kevin McCarthy ,  Leigh M. Tribolet ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US20230197547A1

公开(公告)日：2023-06-22

申请号：US17557945

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L24/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L25/0657 ,  H01L21/56 ,  H01L2224/32145 ,  H01L2225/06517

Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.