公开(公告)号：US20190103346A1

公开(公告)日：2019-04-04

申请号：US15845531

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20180366457A1

公开(公告)日：2018-12-20

申请号：US15781798

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L21/4882 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (TC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

公开(公告)号：US20180286797A1

公开(公告)日：2018-10-04

申请号：US15473317

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Eng Huat Goh

IPC: H01L23/498 ,  H03H7/38 ,  H01L21/48 ,  H01L23/50 ,  H01L23/528 ,  H01L23/522 ,  H01L23/492 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4871 ,  H01L23/4924 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2223/6627 ,  H01L2223/6655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.

公开(公告)号：US10014710B2

公开(公告)日：2018-07-03

申请号：US14964466

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Mark A. Schaecher ,  Teong Guan Yew ,  Eng Huat Goh

IPC: H02J7/02 ,  H02J50/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H02J7/025 ,  H01F27/36 ,  H01F38/14 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/552 ,  H01L25/18 ,  H01L25/50 ,  H02J50/10

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

公开(公告)号：US20160216731A1

公开(公告)日：2016-07-28

申请号：US14604531

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Khai Ern See ,  Damien Weng Kong Chong ,  Min Suet Lim ,  Ping Ping Ooi ,  Chu Aun Lim ,  Jimmy Huat Since Huang ,  Poh Tat Oh ,  Teong Keat Beh ,  Jackson Chung Peng Kong ,  Fern Nee Tan ,  Jenn Chuan Cheng

IPC: G06F1/16 ,  H05K1/18 ,  G06F1/18 ,  G06F13/38

CPC classification number: G06F1/163 ,  G06F1/16 ,  G06F1/1656 ,  G06F1/187 ,  G06F13/38 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

Abstract translation: 实施例一般涉及利用计算机在包装结构上的装置。 计算机的一个实施例包括基板; 一个或多个半导体器件，所述一个或多个半导体器件是直接芯片附着到所述衬底，所述一个或多个半导体器件包括中央处理单元（CPU）; 以及安装在基板上的一个或多个附加部件，其中计算机不包括I / O部件。

公开(公告)号：US20240334600A1

公开(公告)日：2024-10-03

申请号：US18739944

申请日：2024-06-11

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Rijo Kizhakkedathu Avarachan ,  Eng Huat Goh

IPC: H05K1/11 ,  H01L23/00 ,  H05K1/18 ,  H10B80/00

CPC classification number: H05K1/111 ,  H05K1/181 ,  H01L24/16 ,  H01L2224/16227 ,  H05K2201/10159 ,  H10B80/00

Abstract: Printed circuit boards including direct routing from integrated circuit packages are disclosed. An example substrate disclosed herein including a first contact pad array to receive an integrated circuit package, a second contact pad array to receive a memory die, the first contact pad array having a matching arrangement as the second contact pad array, and a layer including a plurality of interconnections extending between the first contact pad array and the second contact pad array.

公开(公告)号：US12002793B2

公开(公告)日：2024-06-04

申请号：US17392189

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Wee Hoe ,  Khang Choong Yong ,  Ping Ping Ooi

IPC: H05K1/02 ,  G06F1/16 ,  G06F1/20 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/02 ,  H05K3/30 ,  H05K7/06 ,  H05K7/20

CPC classification number: H01L25/16 ,  H01L23/48 ,  H01L23/5386 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H05K1/144 ,  H05K1/147 ,  H05K1/181 ,  H05K3/303 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19042 ,  H01L2924/19106 ,  H05K2201/048 ,  H05K2201/055 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2201/10151 ,  H05K2201/10159 ,  H05K2201/10356 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

公开(公告)号：US11699644B2

公开(公告)日：2023-07-11

申请号：US17529093

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/552

Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

公开(公告)号：US11658127B2

公开(公告)日：2023-05-23

申请号：US16454423

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Khang Choong Yong ,  Boon Ping Koh ,  Wil Choon Song ,  Min Suet Lim

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/09

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a package substrate on a substrate, a die on the package substrate, and a conductive stiffener over the package substrate and the substrate. The conductive stiffener surrounds the package substrate, where the conductive stiffener has a top portion and a plurality of sidewalls, and where the top portion is directly disposed on the package substrate, and the sidewalls are vertically disposed on the substrate. The semiconductor package also includes the substrate that has a plurality of conductive pads, where the conductive pads are conductively coupled to a ground source. The conductive stiffener may conductively couple the package substrate to the conductive pads of the substrate. The top portion may have a cavity that surrounds the die, where the top portion is directly disposed on a plurality of outer edges of the package substrate.

公开(公告)号：US11652057B2

公开(公告)日：2023-05-16

申请号：US16405610

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Eng Huat Goh ,  Min Suet Lim ,  Robert Sankman ,  Telesphor Kamgaing ,  Wil Choon Song ,  Boon Ping Koh

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L25/0655

Abstract: Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.