公开(公告)号：WO2003028212A2

公开(公告)日：2003-04-03

申请号：PCT/US2002/031157

申请日：2002-09-27

Applicant: INTEL CORPORATION

Inventor： CHENG, Peng ,  MA, Qing

IPC: H03H9/24

CPC classification number: B81B3/0078 ,  B81B2201/016 ,  B81B2203/019 ,  H03H3/0077 ,  H03H9/2463

Abstract: A micro-electromechanical (MEM) resonator is described that includes a substrate, a microbridge beam structure coupled to the substrate and at least one electrode disposed adjacent to the microbridge beam structure to induce vibration of the beam. The microbridge beam structure includes support sections and a beam formed between the support sections. The center region of the beam has a mass that is less than the mass of regions of the beam adjacent to the support sections.

Abstract translation: 描述了一种微机电（MEM）谐振器，其包括衬底，耦合到衬底的微桥梁结构和邻近微桥梁结构设置的至少一个电极以引起梁的振动。 微桥梁结构包括支撑部分和形成在支撑部分之间的梁。 梁的中心区域的质量小于与支撑部分相邻的梁的区域的质量。

公开(公告)号：WO2003002450A3

公开(公告)日：2003-01-09

申请号：PCT/US2002/020764

申请日：2002-06-27

Applicant: INTEL CORPORATION

Inventor： MA, Qing ,  CHENG, Peng

IPC: B81B3/00

Abstract: A method comprising over an area of a substrate, forming a plurality of three dimensional first structures; following forming the first structures, conformally introducing a sacrificial material over the area of the substrate; introducing a second structural material over the sacrificial material; and removing the sacrificial material. An apparatus comprising a first structure on a substrate; and a second structure on the substrate and separated from the first structure by an unfilled gap defined by the thickness of a removed film.

公开(公告)号：WO2013133827A1

公开(公告)日：2013-09-12

申请号：PCT/US2012/028126

申请日：2012-03-07

Applicant: INTEL CORPORATION ,  MA, Qing ,  SWAN, Johanna M.

Inventor： MA, Qing ,  SWAN, Johanna M.

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81192 ,  H01L2924/00013 ,  H01L2924/12042 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/40 ,  H05K2201/10378 ,  Y10T29/49147 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic substrates. The microelectronic substrate may include a trace routing structure disposed between opposing glass layers. The trace routing structure may comprise one or more dielectric layers having conductive traces formed thereon and therethrough. Also disclosed are embodiments of a microelectronic package including a microelectronic device disposed proximate one glass layer of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects.

Abstract translation: 本说明书的实施例涉及制造微电子基板的领域。 微电子衬底可以包括布置在相对的玻璃层之间的迹线路由结构。 迹线布线结构可以包括一个或多个具有形成在其上并具有导电迹线的电介质层。 还公开了微电子封装的实施例，其包括微电子器件，微电子器件设置在微电子衬底的一个玻璃层附近，并通过多个互连与微电子衬底耦合。

公开(公告)号：WO2013062533A1

公开(公告)日：2013-05-02

申请号：PCT/US2011/057742

申请日：2011-10-25

Applicant: INTEL CORPORATION ,  MA, Qing ,  SWAN, Johanna, M. ,  TAO, Min ,  GEALER, Charles, A. ,  ZARBOCK, Edward, T.

Inventor： MA, Qing ,  SWAN, Johanna, M. ,  TAO, Min ,  GEALER, Charles, A. ,  ZARBOCK, Edward, T.

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/52

CPC classification number: H01L23/49827 ,  B81B2207/012 ,  B81B2207/097 ,  B81B2207/098 ,  B81C1/0023 ,  H01L23/49816 ,  H01L23/49883 ,  H01L24/16 ,  H01L25/165 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/01327 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.

Abstract translation: 传感器芯片与集成电路（IC）芯片的集成。 至少包括第一传感器的第一传感器芯片固定到插入件的第一侧，以将第一传感器密封在第一腔内。 IC芯片被固定到与第一传感器相对的插入件的第二侧，IC芯片通过插入器中的通孔电耦合到第一传感器。 在实施例中，第一传感器包括MEMS器件，并且IC芯片包括放大来自MEMS器件的信号的电路。 插入器可以由玻璃制成，其中第一传感器芯片和IC芯片倒装芯片通过压缩或焊接接合到插入器。 横向互连迹线在插入件上的器件和/或其上插入插入物的PCB之间提供I / O。

公开(公告)号：WO2011126925A3

公开(公告)日：2011-10-13

申请号：PCT/US2011/030808

申请日：2011-03-31

Applicant: INTEL CORPORATION ,  MA, Qing ,  HE, Jun ,  MORROW, Patrick ,  FISCHER, Paul B. ,  BALAKRISHNAN, Sridhar ,  RADHAKRISHNAN, Satish ,  ANDRYUSHCHENKO, Tatyana Tanya ,  XU, Guanghai

Inventor： MA, Qing ,  HE, Jun ,  MORROW, Patrick ,  FISCHER, Paul B. ,  BALAKRISHNAN, Sridhar ,  RADHAKRISHNAN, Satish ,  ANDRYUSHCHENKO, Tatyana Tanya ,  XU, Guanghai

IPC: H05K3/32 ,  H05K1/18

Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

公开(公告)号：WO2011084235A2

公开(公告)日：2011-07-14

申请号：PCT/US2010/056310

申请日：2010-11-11

Applicant: INTEL CORPORATION ,  MA, Qing ,  RAO, Valluri R. ,  TRAN, Quan A. ,  SANKMAN, Robert L. ,  SWAN, Johanna M.

Inventor： MA, Qing ,  RAO, Valluri R. ,  TRAN, Quan A. ,  SANKMAN, Robert L. ,  SWAN, Johanna M.

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H05K1/112 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/15 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K3/0014 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10287 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0108 ,  H05K2203/0228 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的玻璃芯基板的实施例。 玻璃芯基板包括在玻璃芯的相对侧上的玻璃芯和堆积结构。 导电端子可以形成在玻璃芯基板的两侧。 IC芯片可以与衬底的一侧上的端子耦合，而相对侧上的端子可以与诸如电路板的下一级组件耦合。 玻璃芯可以包括其中已经形成导体的单片玻璃，或者玻璃芯可以包括已经连接在一起的两个或更多个玻璃部分，每个部分具有导体。 导体延伸穿过玻璃芯，并且一个或多个导体可以与设置在玻璃芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：WO2007078646A1

公开(公告)日：2007-07-12

申请号：PCT/US2006/047138

申请日：2006-12-06

Applicant: INTEL CORPORATION ,  RAO, Valluri, R. ,  DOROS, Theodore, G. ,  MA, Qing ,  SESHAN, Krishna ,  WANG, Li-Peng

Inventor： RAO, Valluri, R. ,  DOROS, Theodore, G. ,  MA, Qing ,  SESHAN, Krishna ,  WANG, Li-Peng

IPC: H03H3/04 ,  H03H9/58 ,  H03H9/17 ,  H03H9/02

CPC classification number: H03H3/04 ,  H03H3/0076 ,  H03H2003/0428 ,  H03H2003/0478

Abstract: Multiple FBARs may be manufactured on a single wafer and later diced. Ideally, all devices formed in a wafer would have the same resonance frequency. However, due to manufacturing variances, the frequency response of the FBAR devices may vary slightly across the wafer. An RF map may be created to determine zones (50, 52) over the wafer where FBARs in that zone all vary from a target frequency by a similar degree. A tuning layer (40) may be deposited over the wafer. Lithographically patterned features to the tuning layer based on the zones identified by the RF map may be used to correct the FBARs to a target resonance frequency with the FBARs still intact on the wafer.

Abstract translation: 多个FBAR可以在单个晶片上制造并且稍后被切割。 理想地，形成在晶片中的所有器件将具有相同的谐振频率。 然而，由于制造方差，FBAR器件的频率响应可能会在晶圆上略有不同。 可以创建RF映射以确定晶片上的区域（50,52），其中该区域中的FBAR全部从目标频率变化相似程度。 调谐层（40）可以沉积在晶片上。 可以使用基于由RF映射表示的区域的调谐层的光刻图案特征来将FBAR校正到目标谐振频率，同时FBAR在晶片上仍然完整。

公开(公告)号：WO2007041155A2

公开(公告)日：2007-04-12

申请号：PCT/US2006/037646

申请日：2006-09-26

Applicant: INTEL CORPORATION ,  HECK, John ,  MA, Qing

Inventor： HECK, John ,  MA, Qing

IPC: H01L23/13 ,  H01L25/065

CPC classification number: H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20753 ,  H01L2924/00012

Abstract: Microelectronic packages are disclosed. A microelectronic package may include a substrate having first and second sides. Passive components may be located on the first side of the substrate. Interconnects may also be located on the first side of the substrate, and may be electrically coupled with the passive components. Microelectronic components may be located on the first side of the substrate and may be electrically coupled with interconnects. The substrate may include an opening therein. The opening may lead from the second side of the substrate toward the first side of the substrate. A plurality of conductive paths may be at least partially included in the opening. Each of the conductive paths may lead from the second side of the substrate toward the first side of the substrate to communicate electrical signals to interconnects. Methods of making the packages and electronic devices including the packages are also disclosed.

Abstract translation: 公开了微电子封装。 微电子封装可以包括具有第一和第二侧的衬底。 无源元件可以位于基板的第一侧。 互连也可以位于衬底的第一侧上，并且可以与无源元件电耦合。 微电子部件可以位于衬底的第一侧上并且可以与互连电耦合。 衬底可以在其中包括开口。 开口可以从衬底的第二侧面朝向衬底的第一侧面。 多个导电路径可以至少部分地包括在开口中。 每个导电路径可以从衬底的第二侧通向衬底的第一侧，以将电信号传输到互连。 还公开了制造包装和包括包装的电子装置的方法。

公开(公告)号：WO2006127988A1

公开(公告)日：2006-11-30

申请号：PCT/US2006/020407

申请日：2006-05-23

Applicant: INTEL CORPORATION ,  HECK, John ,  MA, Qing

Inventor： HECK, John ,  MA, Qing

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a method for forming a semiconductor device, comprises forming a first aperture (450) and a second aperture (452) in a first surface of the substrate (440) , the first and second apertures being coaxial; forming, in the first aperture, a first conductive path between the first surface of the substrate and a second surface of the substrate; and forming, in the second aperture, a second conductive path between the first surface of the substrate and a second surface of the substrate .

Abstract translation: 在一个实施例中，一种用于形成半导体器件的方法包括在所述衬底（440）的第一表面中形成第一孔（450）和第二孔（452），所述第一和第二孔同轴; 在所述第一孔中形成在所述基板的第一表面和所述基板的第二表面之间的第一导电路径; 以及在所述第二孔中形成在所述基底的所述第一表面和所述基底的第二表面之间的第二导电路径。

公开(公告)号：WO2004036744A2

公开(公告)日：2004-04-29

申请号：PCT/US2003/024142

申请日：2003-08-01

Applicant: INTEL CORPORATION

Inventor： WANG, Li-Peng ,  BAR-SADEH, Eyal ,  RAO, Valluri ,  HECK, John ,  MA, Qing ,  TRAN, Quan ,  TALALYEVSKY, Alexander ,  GINSBURG, Eyal

IPC: H03H3/00

CPC classification number: H03H9/564 ,  H03H3/02 ,  Y10T29/42

Abstract: A film bulk acoustic resonator filter may be formed with a plurality of interconnected series and shunt film bulk acoustic resonators formed on the same membrane. Each of the film bulk acoustic resonators may be formed from a common lower conductive layer which is defined to form the bottom electrode of each film bulk acoustic resonator. A common top conductive layer may be defined to form each top electrode of each film bulk acoustic resonator. A common piezoelectric film layer, that may or may not be patterned, forms a continuous or discontinuous film.

Abstract translation: 薄膜体声波谐振器滤波器可以形成有形成在同一膜上的多个互连串联和分流膜体声波谐振器。 膜体积声谐振器中的每一个可以由限定为形成每个膜体声波谐振器的底部电极的公共下导电层形成。 可以限定共同的顶部导电层以形成每个膜体声波谐振器的每个顶部电极。 可以或可以不被图案化的公共压电膜层形成连续或不连续的膜。