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    Unified hardware and software two-level memory
    32.
    发明授权
    Unified hardware and software two-level memory 有权

    公开(公告)号：US11620060B2

    公开(公告)日：2023-04-04

    申请号：US16235504

    申请日：2018-12-28

    Applicant: INTEL CORPORATION

    Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

    IPC: G06F3/06

    Abstract: Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein an access latency for a near memory device is less than an access latency for a far memory device. The near memory devices store data in data units having addresses in a near memory virtual address space, while the far memory devices store data in data units having addresses in a far memory address space, with a portion of the data being stored on both near and far memory devices. In response to memory read access requests, a determination is made to where data corresponding to the request is located on a near memory device, and if so the data is read from the near memory device; otherwise, the data is read from a far memory device. Memory access patterns are observed, and portions of far memory that are frequently accessed are copied to near memory to reduce access latency for subsequent accesses.

    Enhanced system sleep state support in servers using non-volatile random access memory
    38.
    发明授权
    Enhanced system sleep state support in servers using non-volatile random access memory 有权

    公开(公告)号：US11054876B2

    公开(公告)日：2021-07-06

    申请号：US15823527

    申请日：2017-11-27

    Applicant: Intel Corporation

    Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

    IPC: G06F1/32 ,  G06F1/3206 ,  G06F9/4401 ,  G06F1/3234 ,  G06F1/3287

    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.

    Fast memory initialization
    40.
    发明授权
    Fast memory initialization 有权

    公开(公告)号：US10649690B2

    公开(公告)日：2020-05-12

    申请号：US14998196

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Mohan J. Kumar ,  George Vergis ,  Sarathy Jayakumar

    IPC: G06F11/00 ,  G06F3/06 ,  G06F13/16 ,  G06F21/14 ,  G06F21/53 ,  G06F13/28

    Abstract: In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.

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