公开(公告)号：US11908821B2

公开(公告)日：2024-02-20

申请号：US17563995

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Hiroki Tanaka ,  Robert A. May

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/19 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/20 ,  H01L2224/18

Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

公开(公告)号：US11908802B2

公开(公告)日：2024-02-20

申请号：US17842600

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/00 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2224/97 ,  H01L2224/81

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US11373951B2

公开(公告)日：2022-06-28

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US11101222B2

公开(公告)日：2021-08-24

申请号：US16326679

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta ,  Javier Soto Gonzalez ,  Kwangmo Lim

IPC: H01L23/538 ,  H01L23/00

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US11862552B2

公开(公告)日：2024-01-02

申请号：US17567639

申请日：2022-01-03

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/043 ,  H01F41/046 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/19 ,  H01L24/20 ,  H05K1/00 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16157 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US11735531B2

公开(公告)日：2023-08-22

申请号：US17374886

申请日：2021-07-13

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta ,  Javier Soto Gonzalez ,  Kwangmo Lim

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/00 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/18162

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US11721631B2

公开(公告)日：2023-08-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20220319996A1

公开(公告)日：2022-10-06

申请号：US17842600

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US11251113B2

公开(公告)日：2022-02-15

申请号：US15855453

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L21/48 ,  H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US20210134727A1

公开(公告)日：2021-05-06

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Srinivas V. PIETAMBARAM ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Andrew J. BROWN ,  Lauren A. LINK ,  Prithwish CHATTERJEE

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.